From 3d8064a9f2fd49bffb402b91131087c19ca7d6fc Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Mon, 2 Jul 2018 15:27:13 -0700
Subject: Direct to FIRRTL (#829)

Provide direct conversion from ChiselIR to FIRRTL.
Provide Driver support for dumping ProtoBuf.---
 chiselFrontend/src/main/scala/chisel3/core/Printable.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Printable.scala b/chiselFrontend/src/main/scala/chisel3/core/Printable.scala
index 8c35c33a..7b3d8d4f 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Printable.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Printable.scala
@@ -128,7 +128,7 @@ case class PString(str: String) extends Printable {
     (str replaceAll ("%", "%%"), List.empty)
 }
 /** Superclass for Firrtl format specifiers for Bits */
-sealed abstract class FirrtlFormat(specifier: Char) extends Printable {
+sealed abstract class FirrtlFormat(private[chisel3] val specifier: Char) extends Printable {
   def bits: Bits
   def unpack(ctx: Component): (String, Iterable[String]) = {
     (s"%$specifier", List(bits.ref.fullName(ctx)))
-- 
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