diff options
| author | ducky | 2016-06-01 12:17:25 -0700 |
|---|---|---|
| committer | ducky | 2016-06-08 16:22:27 -0700 |
| commit | 66301b9042530a5265c18c97a0dab9022a0efc50 (patch) | |
| tree | d841f99a375ca7b96297c9d7737e519fd83bf517 /chiselFrontend/src/main | |
| parent | 881ac3cb3a9da0c7827a161238468df4727996f0 (diff) | |
Move chisel/... to chisel/core/..., make chisel/compatibility package/folder, move more things into utils
Diffstat (limited to 'chiselFrontend/src/main')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/Aggregate.scala (renamed from chiselFrontend/src/main/scala/chisel/Aggregate.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/Assert.scala (renamed from chiselFrontend/src/main/scala/chisel/Assert.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/Bits.scala (renamed from chiselFrontend/src/main/scala/chisel/Bits.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/BlackBox.scala (renamed from chiselFrontend/src/main/scala/chisel/BlackBox.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/Data.scala (renamed from chiselFrontend/src/main/scala/chisel/Data.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/Mem.scala (renamed from chiselFrontend/src/main/scala/chisel/Mem.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/Module.scala (renamed from chiselFrontend/src/main/scala/chisel/Module.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/Printf.scala (renamed from chiselFrontend/src/main/scala/chisel/Printf.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/Reg.scala (renamed from chiselFrontend/src/main/scala/chisel/Reg.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/SeqUtils.scala (renamed from chiselFrontend/src/main/scala/chisel/SeqUtils.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/When.scala (renamed from chiselFrontend/src/main/scala/chisel/When.scala) | 0 |
11 files changed, 0 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel/Aggregate.scala b/chiselFrontend/src/main/scala/chisel/core/Aggregate.scala index 4f3f3de0..4f3f3de0 100644 --- a/chiselFrontend/src/main/scala/chisel/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel/core/Aggregate.scala diff --git a/chiselFrontend/src/main/scala/chisel/Assert.scala b/chiselFrontend/src/main/scala/chisel/core/Assert.scala index 0d660bc3..0d660bc3 100644 --- a/chiselFrontend/src/main/scala/chisel/Assert.scala +++ b/chiselFrontend/src/main/scala/chisel/core/Assert.scala diff --git a/chiselFrontend/src/main/scala/chisel/Bits.scala b/chiselFrontend/src/main/scala/chisel/core/Bits.scala index 8ec7c1b9..8ec7c1b9 100644 --- a/chiselFrontend/src/main/scala/chisel/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel/core/Bits.scala diff --git a/chiselFrontend/src/main/scala/chisel/BlackBox.scala b/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala index 1dabc18f..1dabc18f 100644 --- a/chiselFrontend/src/main/scala/chisel/BlackBox.scala +++ b/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala diff --git a/chiselFrontend/src/main/scala/chisel/Data.scala b/chiselFrontend/src/main/scala/chisel/core/Data.scala index c08adf9d..c08adf9d 100644 --- a/chiselFrontend/src/main/scala/chisel/Data.scala +++ b/chiselFrontend/src/main/scala/chisel/core/Data.scala diff --git a/chiselFrontend/src/main/scala/chisel/Mem.scala b/chiselFrontend/src/main/scala/chisel/core/Mem.scala index 5fd8b81e..5fd8b81e 100644 --- a/chiselFrontend/src/main/scala/chisel/Mem.scala +++ b/chiselFrontend/src/main/scala/chisel/core/Mem.scala diff --git a/chiselFrontend/src/main/scala/chisel/Module.scala b/chiselFrontend/src/main/scala/chisel/core/Module.scala index f7f8c0b5..f7f8c0b5 100644 --- a/chiselFrontend/src/main/scala/chisel/Module.scala +++ b/chiselFrontend/src/main/scala/chisel/core/Module.scala diff --git a/chiselFrontend/src/main/scala/chisel/Printf.scala b/chiselFrontend/src/main/scala/chisel/core/Printf.scala index 27b72815..27b72815 100644 --- a/chiselFrontend/src/main/scala/chisel/Printf.scala +++ b/chiselFrontend/src/main/scala/chisel/core/Printf.scala diff --git a/chiselFrontend/src/main/scala/chisel/Reg.scala b/chiselFrontend/src/main/scala/chisel/core/Reg.scala index 0ed320d7..0ed320d7 100644 --- a/chiselFrontend/src/main/scala/chisel/Reg.scala +++ b/chiselFrontend/src/main/scala/chisel/core/Reg.scala diff --git a/chiselFrontend/src/main/scala/chisel/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel/core/SeqUtils.scala index da75edae..da75edae 100644 --- a/chiselFrontend/src/main/scala/chisel/SeqUtils.scala +++ b/chiselFrontend/src/main/scala/chisel/core/SeqUtils.scala diff --git a/chiselFrontend/src/main/scala/chisel/When.scala b/chiselFrontend/src/main/scala/chisel/core/When.scala index 37c59f24..37c59f24 100644 --- a/chiselFrontend/src/main/scala/chisel/When.scala +++ b/chiselFrontend/src/main/scala/chisel/core/When.scala |