diff options
| author | ducky | 2016-06-01 12:17:25 -0700 |
|---|---|---|
| committer | ducky | 2016-06-08 16:22:27 -0700 |
| commit | 66301b9042530a5265c18c97a0dab9022a0efc50 (patch) | |
| tree | d841f99a375ca7b96297c9d7737e519fd83bf517 | |
| parent | 881ac3cb3a9da0c7827a161238468df4727996f0 (diff) | |
Move chisel/... to chisel/core/..., make chisel/compatibility package/folder, move more things into utils
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/Aggregate.scala (renamed from chiselFrontend/src/main/scala/chisel/Aggregate.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/Assert.scala (renamed from chiselFrontend/src/main/scala/chisel/Assert.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/Bits.scala (renamed from chiselFrontend/src/main/scala/chisel/Bits.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/BlackBox.scala (renamed from chiselFrontend/src/main/scala/chisel/BlackBox.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/Data.scala (renamed from chiselFrontend/src/main/scala/chisel/Data.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/Mem.scala (renamed from chiselFrontend/src/main/scala/chisel/Mem.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/Module.scala (renamed from chiselFrontend/src/main/scala/chisel/Module.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/Printf.scala (renamed from chiselFrontend/src/main/scala/chisel/Printf.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/Reg.scala (renamed from chiselFrontend/src/main/scala/chisel/Reg.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/SeqUtils.scala (renamed from chiselFrontend/src/main/scala/chisel/SeqUtils.scala) | 0 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel/core/When.scala (renamed from chiselFrontend/src/main/scala/chisel/When.scala) | 0 | ||||
| -rw-r--r-- | src/main/scala/chisel/compatibility.scala | 14 | ||||
| -rw-r--r-- | src/main/scala/chisel/compatibility/FileSystemUtilities.scala (renamed from src/main/scala/chisel/FileSystemUtilities.scala) | 4 | ||||
| -rw-r--r-- | src/main/scala/chisel/compatibility/Main.scala (renamed from src/main/scala/chisel/Main.scala) | 4 | ||||
| -rw-r--r-- | src/main/scala/chisel/compatibility/throwException.scala (renamed from src/main/scala/chisel/throwException.scala) | 4 | ||||
| -rw-r--r-- | src/main/scala/chisel/package.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/chisel/util/BitPat.scala (renamed from src/main/scala/Chisel/BitPat.scala) | 3 | ||||
| -rw-r--r-- | src/main/scala/chisel/util/ImplicitConversions.scala (renamed from src/main/scala/chisel/ImplicitConversions.scala) | 4 |
18 files changed, 22 insertions, 12 deletions
diff --git a/chiselFrontend/src/main/scala/chisel/Aggregate.scala b/chiselFrontend/src/main/scala/chisel/core/Aggregate.scala index 4f3f3de0..4f3f3de0 100644 --- a/chiselFrontend/src/main/scala/chisel/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel/core/Aggregate.scala diff --git a/chiselFrontend/src/main/scala/chisel/Assert.scala b/chiselFrontend/src/main/scala/chisel/core/Assert.scala index 0d660bc3..0d660bc3 100644 --- a/chiselFrontend/src/main/scala/chisel/Assert.scala +++ b/chiselFrontend/src/main/scala/chisel/core/Assert.scala diff --git a/chiselFrontend/src/main/scala/chisel/Bits.scala b/chiselFrontend/src/main/scala/chisel/core/Bits.scala index 8ec7c1b9..8ec7c1b9 100644 --- a/chiselFrontend/src/main/scala/chisel/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel/core/Bits.scala diff --git a/chiselFrontend/src/main/scala/chisel/BlackBox.scala b/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala index 1dabc18f..1dabc18f 100644 --- a/chiselFrontend/src/main/scala/chisel/BlackBox.scala +++ b/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala diff --git a/chiselFrontend/src/main/scala/chisel/Data.scala b/chiselFrontend/src/main/scala/chisel/core/Data.scala index c08adf9d..c08adf9d 100644 --- a/chiselFrontend/src/main/scala/chisel/Data.scala +++ b/chiselFrontend/src/main/scala/chisel/core/Data.scala diff --git a/chiselFrontend/src/main/scala/chisel/Mem.scala b/chiselFrontend/src/main/scala/chisel/core/Mem.scala index 5fd8b81e..5fd8b81e 100644 --- a/chiselFrontend/src/main/scala/chisel/Mem.scala +++ b/chiselFrontend/src/main/scala/chisel/core/Mem.scala diff --git a/chiselFrontend/src/main/scala/chisel/Module.scala b/chiselFrontend/src/main/scala/chisel/core/Module.scala index f7f8c0b5..f7f8c0b5 100644 --- a/chiselFrontend/src/main/scala/chisel/Module.scala +++ b/chiselFrontend/src/main/scala/chisel/core/Module.scala diff --git a/chiselFrontend/src/main/scala/chisel/Printf.scala b/chiselFrontend/src/main/scala/chisel/core/Printf.scala index 27b72815..27b72815 100644 --- a/chiselFrontend/src/main/scala/chisel/Printf.scala +++ b/chiselFrontend/src/main/scala/chisel/core/Printf.scala diff --git a/chiselFrontend/src/main/scala/chisel/Reg.scala b/chiselFrontend/src/main/scala/chisel/core/Reg.scala index 0ed320d7..0ed320d7 100644 --- a/chiselFrontend/src/main/scala/chisel/Reg.scala +++ b/chiselFrontend/src/main/scala/chisel/core/Reg.scala diff --git a/chiselFrontend/src/main/scala/chisel/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel/core/SeqUtils.scala index da75edae..da75edae 100644 --- a/chiselFrontend/src/main/scala/chisel/SeqUtils.scala +++ b/chiselFrontend/src/main/scala/chisel/core/SeqUtils.scala diff --git a/chiselFrontend/src/main/scala/chisel/When.scala b/chiselFrontend/src/main/scala/chisel/core/When.scala index 37c59f24..37c59f24 100644 --- a/chiselFrontend/src/main/scala/chisel/When.scala +++ b/chiselFrontend/src/main/scala/chisel/core/When.scala diff --git a/src/main/scala/chisel/compatibility.scala b/src/main/scala/chisel/compatibility.scala index 9cdef80d..6e72cdd3 100644 --- a/src/main/scala/chisel/compatibility.scala +++ b/src/main/scala/chisel/compatibility.scala @@ -23,9 +23,6 @@ package object Chisel { val assert = chisel.assert - val BitPat = chisel.BitPat - type BitPat = chisel.BitPat - type Element = chisel.Element type Bits = chisel.Bits val Bits = chisel.Bits @@ -59,10 +56,10 @@ package object Chisel { type BackendCompilationUtilities = chisel.BackendCompilationUtilities val Driver = chisel.Driver - type FileSystemUtilities = chisel.FileSystemUtilities - val ImplicitConversions = chisel.ImplicitConversions - val chiselMain = chisel.chiselMain - val throwException = chisel.throwException + type FileSystemUtilities = chisel.compatibility.FileSystemUtilities + val ImplicitConversions = chisel.util.ImplicitConversions + val chiselMain = chisel.compatibility.chiselMain + val throwException = chisel.compatibility.throwException object testers { @@ -77,6 +74,9 @@ package object Chisel { val log2Floor = chisel.util.log2Floor val isPow2 = chisel.util.isPow2 + val BitPat = chisel.util.BitPat + type BitPat = chisel.util.BitPat + type ArbiterIO[T <: Data] = chisel.util.ArbiterIO[T] type LockingArbiterLike[T <: Data] = chisel.util.LockingArbiterLike[T] type LockingRRArbiter[T <: Data] = chisel.util.LockingRRArbiter[T] diff --git a/src/main/scala/chisel/FileSystemUtilities.scala b/src/main/scala/chisel/compatibility/FileSystemUtilities.scala index f100eaf6..d12e627d 100644 --- a/src/main/scala/chisel/FileSystemUtilities.scala +++ b/src/main/scala/chisel/compatibility/FileSystemUtilities.scala @@ -1,6 +1,8 @@ // See LICENSE for license details. -package chisel +package chisel.compatibility + +import chisel._ @deprecated("FileSystemUtilities doesn't exist in chisel3", "3.0.0") trait FileSystemUtilities { diff --git a/src/main/scala/chisel/Main.scala b/src/main/scala/chisel/compatibility/Main.scala index 79e5c9ca..9072bfcf 100644 --- a/src/main/scala/chisel/Main.scala +++ b/src/main/scala/chisel/compatibility/Main.scala @@ -1,9 +1,11 @@ // See LICENSE for license details. -package chisel +package chisel.compatibility import java.io.File +import chisel._ + @deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain { def apply[T <: Module](args: Array[String], gen: () => T): Unit = Predef.assert(false, "No more chiselMain in Chisel3") diff --git a/src/main/scala/chisel/throwException.scala b/src/main/scala/chisel/compatibility/throwException.scala index fdd62c7e..3b9fd06e 100644 --- a/src/main/scala/chisel/throwException.scala +++ b/src/main/scala/chisel/compatibility/throwException.scala @@ -1,6 +1,8 @@ // See LICENSE for license details. -package chisel +package chisel.compatibility + +import chisel._ @deprecated("throwException doesn't exist in Chisel3", "3.0.0") @throws(classOf[Exception]) diff --git a/src/main/scala/chisel/package.scala b/src/main/scala/chisel/package.scala index 1abbc74f..b6036c75 100644 --- a/src/main/scala/chisel/package.scala +++ b/src/main/scala/chisel/package.scala @@ -3,6 +3,7 @@ package object chisel { import internal.firrtl.Width import internal.sourceinfo.{SourceInfo, SourceInfoTransform} + import util.BitPat implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal { def U: UInt = UInt(x, Width()) diff --git a/src/main/scala/Chisel/BitPat.scala b/src/main/scala/chisel/util/BitPat.scala index a6833ed2..13bbe1b0 100644 --- a/src/main/scala/Chisel/BitPat.scala +++ b/src/main/scala/chisel/util/BitPat.scala @@ -1,9 +1,10 @@ // See LICENSE for license details. -package chisel +package chisel.util import scala.language.experimental.macros +import chisel._ import chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform} object BitPat { diff --git a/src/main/scala/chisel/ImplicitConversions.scala b/src/main/scala/chisel/util/ImplicitConversions.scala index f786d4f1..846c0cbd 100644 --- a/src/main/scala/chisel/ImplicitConversions.scala +++ b/src/main/scala/chisel/util/ImplicitConversions.scala @@ -1,6 +1,8 @@ // See LICENSE for license details. -package chisel +package chisel.util + +import chisel._ object ImplicitConversions { implicit def intToUInt(x: Int): UInt = UInt(x) |
