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authorChick Markley2020-02-03 09:38:44 -0800
committerGitHub2020-02-03 09:38:44 -0800
commit4f1f638663a7176ac28d95d71c14a37021314c3b (patch)
treeb1377a66921f953458523b54b531298f56beeb69 /chiselFrontend/src/main
parentf1c4395bd608234fef5a60d8851036d1acb2382f (diff)
parentefc40252631869531e79f4d8490113d18e75cc1d (diff)
Merge pull request #1285 from freechipsproject/add-asbool-to-clock
Add method asBool to Clock.
Diffstat (limited to 'chiselFrontend/src/main')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/Clock.scala7
1 files changed, 6 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/Clock.scala b/chiselFrontend/src/main/scala/chisel3/Clock.scala
index 87674e7b..d7975b1e 100644
--- a/chiselFrontend/src/main/scala/chisel3/Clock.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Clock.scala
@@ -2,7 +2,8 @@
package chisel3
-import chisel3.internal.Builder.{pushOp}
+import scala.language.experimental.macros
+import chisel3.internal.Builder.pushOp
import chisel3.internal.firrtl._
import chisel3.internal.sourceinfo._
import chisel3.internal.firrtl.PrimOp.AsUIntOp
@@ -30,6 +31,10 @@ sealed class Clock(private[chisel3] val width: Width = Width(1)) extends Element
/** Not really supported */
def toPrintable: Printable = PString("CLOCK")
+ /** Returns the contents of the clock wire as a [[Bool]]. */
+ final def asBool(): Bool = macro SourceInfoTransform.noArg
+ def do_asBool(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = this.asUInt().asBool()
+
override def do_asUInt(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): UInt = pushOp(DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref)) // scalastyle:ignore line.size.limit
private[chisel3] override def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo,
compileOptions: CompileOptions): Unit = {