diff options
| author | Jack Koenig | 2018-06-01 12:16:11 -0700 |
|---|---|---|
| committer | GitHub | 2018-06-01 12:16:11 -0700 |
| commit | d0cdd3b4c3713bb7454868fac7fa9c43bae2332c (patch) | |
| tree | 1b0ec2359ae56b3f2be006a09eca50a6b430ede4 /chiselFrontend/src/main/scala/chisel3 | |
| parent | 7df245e7c01d28de51d8dc27a35756e7f5eb4331 (diff) | |
Literals set their ref so they no longer get named (#826)
Fixes #763
Add tests for #763 and #472
This has a few implications
* Constructing a literal no longer increments _T_ suffixes
* Internally, wrapping a literal Bits in Node(...) will work
* Literal Bools work in withReset/withClockAndReset
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Bits.scala | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index b3091db3..dd99d822 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -67,6 +67,9 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg]) // Arguments for: self-checking code (can't do arithmetic on bits) // Arguments against: generates down to a FIRRTL UInt anyways + // If this is a literal, setRef so that we don't allocate a name + litArg.foreach(setRef) + // Only used for in a few cases, hopefully to be removed private[core] def cloneTypeWidth(width: Width): this.type |