diff options
| author | Jack Koenig | 2017-04-02 18:29:17 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2017-04-02 18:29:17 -0700 |
| commit | bc05b7dadbd875c5a1ffb1448c36fcdb429386ab (patch) | |
| tree | 086e4080d662237b0df952eb0cd243de095c38d0 /chiselFrontend/src/main/scala/chisel3 | |
| parent | d72bcca424808268df08466ea69e394f8dafcd57 (diff) | |
Make Module instantiations draw clock from Builder instead of parent (#568)
Fixes #567
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Module.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index 1388fb80..b838eb05 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -190,8 +190,8 @@ extends HasId { _parent match { case Some(p) => { pushCommand(DefInvalid(sourceInfo, io.ref)) // init instance inputs - clock := override_clock.getOrElse(p.clock) - reset := override_reset.getOrElse(p.reset) + clock := override_clock.getOrElse(Builder.forcedClock) + reset := override_reset.getOrElse(Builder.forcedReset) this } case None => this |