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| author | Andrew Waterman | 2017-02-24 00:12:19 -0800 |
|---|---|---|
| committer | Jack Koenig | 2017-03-08 11:27:04 -0600 |
| commit | 9734a42a03036e0ce329bb507b581633e86e9693 (patch) | |
| tree | ec9ed07713bcc274d5e41f61166d6025e0adf6bc /chiselFrontend/src/main/scala/chisel3 | |
| parent | 9cad9ec21ac7a9a8c463e2c694b6285269982a84 (diff) | |
Fix the widths of QueueIO.count and ArbiterIO.chosen for entries=0
Both should be zero-width wires.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3')
0 files changed, 0 insertions, 0 deletions