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authorAdam Izraelevitz2017-05-12 14:09:14 -0700
committerGitHub2017-05-12 14:09:14 -0700
commit5977bd68f9378d9875a2f494195375c1dae442e5 (patch)
tree627d71c8a83205e40ae357ed2faefbca85fd246a /chiselFrontend/src/main/scala/chisel3
parent8baa2ab806be1aa85a7a1da7b348726da1bd1d19 (diff)
Changed multiplication of SInt and UInt (#611)
Enables changing FIRRTL's IR to only accept multiplication of identical types.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Bits.scala7
1 files changed, 5 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index e8423a99..7de7be09 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -594,8 +594,11 @@ sealed class SInt private[core] (width: Width, lit: Option[SLit] = None)
binop(sourceInfo, SInt(this.width), RemOp, that)
final def * (that: UInt): SInt = macro SourceInfoTransform.thatArg
- def do_* (that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt =
- binop(sourceInfo, SInt(this.width + that.width), TimesOp, that)
+ def do_* (that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = {
+ val thatToSInt = that.zext()
+ val result = binop(sourceInfo, SInt(this.width + thatToSInt.width), TimesOp, thatToSInt)
+ result.tail(1).asSInt
+ }
/** add (width +1) operator */
final def +& (that: SInt): SInt = macro SourceInfoTransform.thatArg