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authorJim Lawson2018-07-31 14:11:33 -0700
committerJack Koenig2018-07-31 14:11:33 -0700
commit64a8f52c48905e9bf28e709cde2de89215a35c80 (patch)
tree0ce0f63a3891fed71810f81866ca5b7ee957b3c2 /chiselFrontend/src/main/scala/chisel3/core
parentfea4f3a80d2ed5d4735ef33558bebbab290290fb (diff)
Ensure names work for bundles and literals. (#853)
Fixes #852
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Bits.scala15
1 files changed, 7 insertions, 8 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 35f6c978..10b6ec8e 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -604,8 +604,7 @@ trait UIntFactory {
val lit = ULit(value, width)
val result = new UInt(lit.width)
// Bind result to being an Literal
- result.bind(ElementLitBinding(lit))
- result
+ lit.bindLitArg(result)
}
/** Create a UInt with the specified range */
@@ -757,8 +756,7 @@ trait SIntFactory {
protected[chisel3] def Lit(value: BigInt, width: Width): SInt = {
val lit = SLit(value, width)
val result = new SInt(lit.width)
- result.bind(ElementLitBinding(lit))
- result
+ lit.bindLitArg(result)
}
}
@@ -828,8 +826,9 @@ trait BoolFactory {
*/
protected[chisel3] def Lit(x: Boolean): Bool = {
val result = new Bool()
- result.bind(ElementLitBinding(ULit(if (x) 1 else 0, Width(1))))
- result
+ val lit = ULit(if (x) 1 else 0, Width(1))
+ // Ensure we have something capable of generating a name.
+ lit.bindLitArg(result)
}
}
@@ -1086,8 +1085,8 @@ object FixedPoint {
def apply(value: BigInt, width: Width, binaryPoint: BinaryPoint): FixedPoint = {
val lit = FPLit(value, width, binaryPoint)
val newLiteral = new FixedPoint(lit.width, lit.binaryPoint)
- newLiteral.bind(ElementLitBinding(lit))
- newLiteral
+ // Ensure we have something capable of generating a name.
+ lit.bindLitArg(newLiteral)
}
/**