diff options
| author | Jack | 2017-01-30 22:42:57 -0800 |
|---|---|---|
| committer | Jack Koenig | 2017-01-31 11:30:28 -0800 |
| commit | 3ef63639284b2b56f415e1540c58d85d88c360db (patch) | |
| tree | 5ab5802bcd1ec2a86ef23a67b6d1249488425deb /chiselFrontend/src/main/scala/chisel3/core | |
| parent | f8408623e13149ccd4bfae443d916eeb9c5a2146 (diff) | |
Make Module and Bundle properly use empty namespaces
Fix default suggested name of Module instances (now based on desired name
rather than actual assigned name).
Remove parent/child relationship from Namespace.
Previously, Module and Bundle namespaces were "children" of the Module
definition namespace. This could lead to collisions that would give unexpected
names for module instances or Bundle elements. In particular, otherwise
identical modules that instantiate other identical modules in such a way that
the instance cannot be named via reflection would not be deduplicated because
the names of the instances would collide with the names of the modules in the
Builder.globalNamespace.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 5 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Module.scala | 5 |
2 files changed, 7 insertions, 3 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index 732bf8fc..efb30326 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -374,7 +374,10 @@ abstract class Record extends Aggregate { // NOTE: This sets up dependent references, it can be done before closing the Module private[chisel3] override def _onModuleClose: Unit = { // scalastyle:ignore method.name - val _namespace = Builder.globalNamespace.child + // Since Bundle names this via reflection, it is impossible for two elements to have the same + // identifier; however, Namespace sanitizes identifiers to make them legal for Firrtl/Verilog + // which can cause collisions + val _namespace = Namespace.empty for ((name, elt) <- elements) { elt.setRef(this, _namespace.name(name)) } } diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index ca7c8abd..de13c078 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -113,7 +113,8 @@ extends HasId { Port(iodef) } - private[core] val _namespace = Builder.globalNamespace.child + // Fresh Namespace because in Firrtl, Modules namespaces are disjoint with the global namespace + private[core] val _namespace = Namespace.empty private[chisel3] val _commands = ArrayBuffer[Command]() private[core] val _ids = ArrayBuffer[HasId]() Builder.currentModule = Some(this) @@ -210,7 +211,7 @@ extends HasId { // For Module instances we haven't named, suggest the name of the Module _ids foreach { - case m: Module => m.suggestName(m.name) + case m: Module => m.suggestName(m.desiredName) case _ => } |
