diff options
| author | Wesley W. Terpstra | 2017-02-17 20:20:28 +0100 |
|---|---|---|
| committer | Jack Koenig | 2017-02-27 16:08:12 -0800 |
| commit | 3b2a99530052c5e06b9179754a8dfe3e0d53e612 (patch) | |
| tree | 6b758411e5ca22726109b5e731618615d7aa6039 /chiselFrontend/src/main/scala/chisel3/core | |
| parent | fd1887208fe41e986d90308c25af28172c6b5aa6 (diff) | |
Record: allow elements to start with a digit
This is necessary for user-defined Record-derived types to retain
the same signal name as they would using a Vec.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index 131719f1..92cf658d 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -411,7 +411,7 @@ abstract class Record extends Aggregate { // identifier; however, Namespace sanitizes identifiers to make them legal for Firrtl/Verilog // which can cause collisions val _namespace = Namespace.empty - for ((name, elt) <- elements) { elt.setRef(this, _namespace.name(name)) } + for ((name, elt) <- elements) { elt.setRef(this, _namespace.name(name, leadingDigitOk=true)) } } private[chisel3] final def allElements: Seq[Element] = elements.toIndexedSeq.flatMap(_._2.allElements) |