From 3b2a99530052c5e06b9179754a8dfe3e0d53e612 Mon Sep 17 00:00:00 2001
From: Wesley W. Terpstra
Date: Fri, 17 Feb 2017 20:20:28 +0100
Subject: Record: allow elements to start with a digit

This is necessary for user-defined Record-derived types to retain
the same signal name as they would using a Vec.
---
 chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 131719f1..92cf658d 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -411,7 +411,7 @@ abstract class Record extends Aggregate {
     // identifier; however, Namespace sanitizes identifiers to make them legal for Firrtl/Verilog
     // which can cause collisions
     val _namespace = Namespace.empty
-    for ((name, elt) <- elements) { elt.setRef(this, _namespace.name(name)) }
+    for ((name, elt) <- elements) { elt.setRef(this, _namespace.name(name, leadingDigitOk=true)) }
   }
 
   private[chisel3] final def allElements: Seq[Element] = elements.toIndexedSeq.flatMap(_._2.allElements)
-- 
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