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authorJim Lawson2016-07-19 16:52:27 -0700
committerJim Lawson2016-07-19 16:52:27 -0700
commitf81202b896d30d90075be487895befa009b11733 (patch)
treeeba7bd56990788ecc6f68cca37a62e699ef57bf7 /chiselFrontend/src/main/scala/chisel3/core/Reg.scala
parent01e14c8c885527861152443f1233fa77b03cb8b5 (diff)
Fixes for only connectwrap version.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Reg.scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Reg.scala15
1 files changed, 8 insertions, 7 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
index df760b5c..b46b96ef 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
@@ -12,16 +12,18 @@ object Reg {
init: T = null): T = {
if (t ne null) {
Binding.checkUnbound(t, s"t ($t) must be unbound Type. Try using newType?")
- t.newType
- } else if (next ne null) next.cloneTypeWidth(Width())
- else if (init ne null) {
+ t.cloneType
+ } else if (next ne null) {
+ next.cloneTypeWidth(Width())
+ } else if (init ne null) {
init.litArg match {
- // For e.g. Reg(init=0.asUInt(k)), fix the Reg's width to k
- case Some(lit) if lit.forcedWidth => init.newType
+ // For e.g. Reg(init=UInt(0, k)), fix the Reg's width to k
+ case Some(lit) if lit.forcedWidth => init.cloneType
case _ => init.cloneTypeWidth(Width())
}
+ } else {
+ throwException("cannot infer type")
}
- else throw new Exception("cannot infer type")
}
/** Creates a register with optional next and initialization values.
@@ -72,7 +74,6 @@ init: T = null): T = {
Binding.checkSynthesizable(next, s"'next' ($next)")
x := next
}
-
x
}
}