Merge in "complete" versions of Mem, Reg.

1 files changed, 14 insertions, 8 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
index 14ae9650..df760b5c 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
@@ -11,18 +11,17 @@ object Reg {
   private[core] def makeType[T <: Data](t: T = null, next: T = null,
 init: T = null): T = {
     if (t ne null) {
-      t.cloneType
-    } else if (next ne null) {
-      next.cloneTypeWidth(Width())
-    } else if (init ne null) {
+      Binding.checkUnbound(t, s"t ($t) must be unbound Type. Try using newType?")
+      t.newType
+    } else if (next ne null) next.cloneTypeWidth(Width())
+    else if (init ne null) {
       init.litArg match {
-        // For e.g. Reg(init=UInt(0, k)), fix the Reg's width to k
-        case Some(lit) if lit.forcedWidth => init.cloneType
+        // For e.g. Reg(init=0.asUInt(k)), fix the Reg's width to k
+        case Some(lit) if lit.forcedWidth => init.newType
         case _ => init.cloneTypeWidth(Width())
       }
-    } else {
-      throwException("cannot infer type")
     }
+    else throw new Exception("cannot infer type")
   }
 
   /** Creates a register with optional next and initialization values.
@@ -59,14 +58,21 @@ init: T = null): T = {
     // system improves, this may be changed.
     val x = makeType(t, next, init)
     val clock = Node(x._parent.get.clock) // TODO multi-clock
+
+    // Bind each element of x to being a Reg
+    Binding.bind(x, RegBinder(Builder.forcedModule), "Error: t")
+
     if (init == null) {
       pushCommand(DefReg(sourceInfo, x, clock))
     } else {
+      Binding.checkSynthesizable(init, s"'init' ($init)")
       pushCommand(DefRegInit(sourceInfo, x, clock, Node(x._parent.get.reset), init.ref))
     }
     if (next != null) {
+      Binding.checkSynthesizable(next, s"'next' ($next)")
       x := next
     }
+
     x
   }
 }