Module Hierarchy Refactor (#469)

1 files changed, 1 insertions, 0 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
index 81210f45..2052e95a 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
@@ -64,6 +64,7 @@ object printf { // scalastyle:ignore object.name
     val clock = Builder.forcedClock
     pushCommand(Printf(sourceInfo, Node(clock), pable))
   }
+
   private[chisel3] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo): Unit =
     printfWithoutReset(Printable.pack(fmt, data:_*))
 }