From e07248b8f6022fafdb84f5d1c0ebe3fc90a5475a Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Thu, 13 Apr 2017 22:59:00 -0700
Subject: Module Hierarchy Refactor (#469)

---
 chiselFrontend/src/main/scala/chisel3/core/Printf.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Printf.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
index 81210f45..2052e95a 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
@@ -64,6 +64,7 @@ object printf { // scalastyle:ignore object.name
     val clock = Builder.forcedClock
     pushCommand(Printf(sourceInfo, Node(clock), pable))
   }
+
   private[chisel3] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo): Unit =
     printfWithoutReset(Printable.pack(fmt, data:_*))
 }
-- 
cgit v1.2.3