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| author | Andrew Waterman | 2017-02-24 00:08:18 -0800 |
|---|---|---|
| committer | Jack Koenig | 2017-03-08 11:27:04 -0600 |
| commit | 9cad9ec21ac7a9a8c463e2c694b6285269982a84 (patch) | |
| tree | 03afab0e61f6891f9269d68d56a8ef0b13d3b31f /chiselFrontend/src/main/scala/chisel3/core/Module.scala | |
| parent | 246c2e8336c19d39bfb92dc8f2ee730a2ac4c55b (diff) | |
Improve Reverse's exception behavior; avoid log2Up
Provide a better error message when length < 0.
Change log2Up in log2Ceil, which has no effect, since the argument
is always at least 2.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')
0 files changed, 0 insertions, 0 deletions