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| author | Jack Koenig | 2016-12-21 14:33:07 -0800 |
|---|---|---|
| committer | Jack Koenig | 2017-02-08 18:00:32 -0800 |
| commit | 66a72ff64c46d8a9fdade77223de62b4dcfe2825 (patch) | |
| tree | 8ff97057072ed7ec1e1c64b3f1db774e2c09f99e /chiselFrontend/src/main/scala/chisel3/core/Module.scala | |
| parent | 132b80edee2fb8e730d3b6f5eb5f36051a819525 (diff) | |
Add Analog type
Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')
0 files changed, 0 insertions, 0 deletions