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| author | Albert Magyar | 2017-08-17 17:55:44 -0700 |
|---|---|---|
| committer | Jack Koenig | 2017-08-17 17:55:44 -0700 |
| commit | 6297e00aa845cf6cc1275c05d313f3237e69de9d (patch) | |
| tree | 05363bfee404a441d5a759e292bd894c1e2db8a6 /chiselFrontend/src/main/scala/chisel3/core/Module.scala | |
| parent | 6e12ed9fd7a771eb30f44b8e1c4ab33f6ad8e0a6 (diff) | |
Use firrtl elses in elsewhen/otherwise case emission (#510)
Preprocess chisel3 IR before emission to determing whether
whens have alternatives.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')
0 files changed, 0 insertions, 0 deletions