Merge pull request #265 from ucb-bar/gsdt

Gsdt - Fixup to Chisel connections and direction - PR 200 revisited.

1 files changed, 163 insertions, 41 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 197b6181..3f21a34c 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -14,13 +14,103 @@ sealed abstract class Direction(name: String) {
   override def toString: String = name
   def flip: Direction
 }
-object INPUT  extends Direction("input") { override def flip: Direction = OUTPUT }
-object OUTPUT extends Direction("output") { override def flip: Direction = INPUT }
-object NO_DIR extends Direction("?") { override def flip: Direction = NO_DIR }
+object Direction {
+  object Input  extends Direction("input") { override def flip: Direction = Output }
+  object Output extends Direction("output") { override def flip: Direction = Input }
+  object Unspecified extends Direction("unspecified") { override def flip: Direction = Input }
+}
+
+@deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3")
+object debug {  // scalastyle:ignore object.name
+  def apply (arg: Data): Data = arg
+}
 
-/** Mixing in this trait flips the direction of an Aggregate. */
-trait Flipped extends Data {
-  this.overrideDirection(_.flip, !_)
+object DataMirror {
+  def widthOf(target: Data): Width = target.width
+}
+
+/**
+* Input, Output, and Flipped are used to define the directions of Module IOs.
+*
+* Note that they currently clone their source argument, including its bindings.
+*
+* Thus, an error will be thrown if these are used on bound Data
+*/
+object Input {
+  def apply[T<:Data](source: T): T = {
+    val target = source.chiselCloneType
+    Data.setFirrtlDirection(target, Direction.Input)
+    Binding.bind(target, InputBinder, "Error: Cannot set as input ")
+  }
+}
+object Output {
+  def apply[T<:Data](source: T): T = {
+    val target = source.chiselCloneType
+    Data.setFirrtlDirection(target, Direction.Output)
+    Binding.bind(target, OutputBinder, "Error: Cannot set as output ")
+  }
+}
+object Flipped {
+  def apply[T<:Data](source: T): T = {
+    val target = source.chiselCloneType
+    Data.setFirrtlDirection(target, Data.getFirrtlDirection(source).flip)
+    Binding.bind(target, FlippedBinder, "Error: Cannot flip ")
+  }
+}
+
+object Data {
+  /**
+  * This function returns true if the FIRRTL type of this Data should be flipped
+  * relative to other nodes.
+  *
+  * Note that the current scheme only applies Flip to Elements or Vec chains of
+  * Elements.
+  *
+  * A Bundle is never marked flip, instead preferring its root fields to be marked
+  *
+  * The Vec check is due to the fact that flip must be factored out of the vec, ie:
+  * must have flip field: Vec(UInt) instead of field: Vec(flip UInt)
+  */
+  private[chisel3] def isFlipped(target: Data): Boolean = target match {
+    case (element: Element) => element.binding.direction == Some(Direction.Input)
+    case (vec: Vec[Data @unchecked]) => isFlipped(vec.sample_element)
+    case (bundle: Bundle) => false
+  }
+
+  /** This function returns the "firrtl" flipped-ness for the specified object.
+    *
+    * @param target the object for which we want the "firrtl" flipped-ness.
+    */
+  private[chisel3] def isFirrtlFlipped(target: Data): Boolean = {
+    Data.getFirrtlDirection(target) == Direction.Input
+  }
+
+  /** This function gets the "firrtl" direction for the specified object.
+    *
+    * @param target the object for which we want to get the "firrtl" direction.
+    */
+  private[chisel3] def getFirrtlDirection(target: Data): Direction = target match {
+    case (vec: Vec[Data @unchecked]) => vec.sample_element.firrtlDirection
+    case _ => target.firrtlDirection
+  }
+
+  /** This function sets the "firrtl" direction for the specified object.
+    *
+    * @param target the object for which we want to set the "firrtl" direction.
+    */
+  private[chisel3] def setFirrtlDirection(target: Data, direction: Direction): Unit = target match {
+    case (vec: Vec[Data @unchecked]) => vec.sample_element.firrtlDirection = direction
+    case _ => target.firrtlDirection = direction
+  }
+
+  implicit class AddDirectionToData[T<:Data](val target: T) extends AnyVal {
+    @deprecated("Input(Data) should be used over Data.asInput", "gchisel")
+    def asInput: T = Input(target)
+    @deprecated("Output(Data) should be used over Data.asOutput", "gchisel")
+    def asOutput: T = Output(target)
+    @deprecated("Flipped(Data) should be used over Data.flip", "gchisel")
+    def flip(): T = Flipped(target)
+  }
 }
 
 /** This forms the root of the type system for wire data types. The data value
@@ -28,42 +118,56 @@ trait Flipped extends Data {
   * time) of bits, and must have methods to pack / unpack structured data to /
   * from bits.
   */
-abstract class Data(dirArg: Direction) extends HasId {
-  def dir: Direction = dirVar
-
-  // Sucks this is mutable state, but cloneType doesn't take a Direction arg
-  private var isFlipVar = dirArg == INPUT
-  private var dirVar = dirArg
-  private[core] def isFlip = isFlipVar
-
-  private[core] def overrideDirection(newDir: Direction => Direction,
-                                        newFlip: Boolean => Boolean): this.type = {
-    this.isFlipVar = newFlip(this.isFlipVar)
-    for (field <- this.flatten)
-      (field: Data).dirVar = newDir((field: Data).dirVar)
-    this
-  }
-  def asInput: this.type = cloneType.overrideDirection(_ => INPUT, _ => true)
-  def asOutput: this.type = cloneType.overrideDirection(_ => OUTPUT, _ => false)
-  def flip(): this.type = cloneType.overrideDirection(_.flip, !_)
+abstract class Data extends HasId {
+  // Return ALL elements at root of this type.
+  // Contasts with flatten, which returns just Bits
+  private[chisel3] def allElements: Seq[Element]
 
   private[core] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     throwException(s"cannot connect ${this} and ${that}")
-  private[core] def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
-    pushCommand(Connect(sourceInfo, this.lref, that.ref))
-  private[core] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
-    pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))
-  private[core] def lref: Node = Node(this)
+  private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = {
+    Binding.checkSynthesizable(this, s"'this' ($this)")
+    Binding.checkSynthesizable(that, s"'that' ($that)")
+    try {
+      MonoConnect.connect(sourceInfo, connectCompileOptions, this, that, Builder.forcedModule)
+    } catch {
+      case MonoConnect.MonoConnectException(message) =>
+        throwException(
+          s"Connection between sink ($this) and source ($that) failed @$message"
+        )
+    }
+  }
+  private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = {
+    Binding.checkSynthesizable(this, s"'this' ($this)")
+    Binding.checkSynthesizable(that, s"'that' ($that)")
+    try {
+      BiConnect.connect(sourceInfo, connectCompileOptions, this, that, Builder.forcedModule)
+    } catch {
+      case BiConnect.BiConnectException(message) =>
+        throwException(
+          s"Connection between left ($this) and source ($that) failed @$message"
+        )
+    }
+  }
+  private[chisel3] def lref: Node = Node(this)
   private[chisel3] def ref: Arg = if (isLit) litArg.get else lref
   private[core] def cloneTypeWidth(width: Width): this.type
   private[chisel3] def toType: String
   private[core] def width: Width
 
-  def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this badConnect that
-
-  def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = this badConnect that
-
   def cloneType: this.type
+  def chiselCloneType: this.type = {
+    // Call the user-supplied cloneType method
+    val clone = this.cloneType
+    Data.setFirrtlDirection(clone, Data.getFirrtlDirection(this))
+    //TODO(twigg): Do recursively for better error messages
+    for((clone_elem, source_elem) <- clone.allElements zip this.allElements) {
+      clone_elem.binding = UnboundBinding(source_elem.binding.direction)
+    }
+    clone
+  }
+  final def := (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.connect(that)(sourceInfo, connectionCompileOptions)
+  final def <> (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.bulkConnect(that)(sourceInfo, connectionCompileOptions)
   def litArg(): Option[LitArg] = None
   def litValue(): BigInt = litArg.get.num
   def isLit(): Boolean = litArg.isDefined
@@ -101,7 +205,7 @@ abstract class Data(dirArg: Direction) extends HasId {
 
   def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo): this.type = {
     var i = 0
-    val wire = Wire(this.cloneType)
+    val wire = Wire(this.chiselCloneType)
     val bits =
       if (that.width.known && that.width.get >= wire.width.get) {
         that
@@ -134,6 +238,11 @@ abstract class Data(dirArg: Direction) extends HasId {
   def do_asUInt(implicit sourceInfo: SourceInfo): UInt =
     SeqUtils.do_asUInt(this.flatten)(sourceInfo)
 
+  // firrtlDirection is the direction we report to firrtl.
+  // It maintains the user-specified value (as opposed to the "actual" or applied/propagated value).
+  // NOTE: This should only be used for emitting acceptable firrtl.
+  // The Element.dir should be used for any tests involving direction.
+  private var firrtlDirection: Direction = Direction.Unspecified
   /** Default pretty printing */
   def toPrintable: Printable
 }
@@ -150,10 +259,15 @@ object Wire {
     do_apply(t, init)(UnlocatableSourceInfo)
 
   def do_apply[T <: Data](t: T, init: T)(implicit sourceInfo: SourceInfo): T = {
-    val x = Reg.makeType(t, null.asInstanceOf[T], init)
+    val x = Reg.makeType(chisel3.core.ExplicitCompileOptions.NotStrict, t, null.asInstanceOf[T], init)
+
+    // Bind each element of x to being a Wire
+    Binding.bind(x, WireBinder(Builder.forcedModule), "Error: t")
+
     pushCommand(DefWire(sourceInfo, x))
     pushCommand(DefInvalid(sourceInfo, x.ref))
     if (init != null) {
+      Binding.checkSynthesizable(init, s"'init' ($init)")
       x := init
     }
     x
@@ -161,19 +275,27 @@ object Wire {
 }
 
 object Clock {
-  def apply(dir: Direction = NO_DIR): Clock = new Clock(dir)
+  def apply(): Clock = new Clock
+  def apply(dir: Direction): Clock = {
+    val result = apply()
+    dir match {
+      case Direction.Input => Input(result)
+      case Direction.Output => Output(result)
+      case Direction.Unspecified => result
+    }
+  }
 }
 
 // TODO: Document this.
-sealed class Clock(dirArg: Direction) extends Element(dirArg, Width(1)) {
-  def cloneType: this.type = Clock(dirArg).asInstanceOf[this.type]
+sealed class Clock extends Element(Width(1)) {
+  def cloneType: this.type = Clock().asInstanceOf[this.type]
   private[chisel3] override def flatten: IndexedSeq[Bits] = IndexedSeq()
   private[core] def cloneTypeWidth(width: Width): this.type = cloneType
   private[chisel3] def toType = "Clock"
 
-  override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
-    case _: Clock => this connect that
-    case _ => this badConnect that
+  override def connect (that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = that match {
+    case _: Clock => super.connect(that)(sourceInfo, connectCompileOptions)
+    case _ => super.badConnect(that)(sourceInfo)
   }
 
   /** Not really supported */