From c5f9ea3133ef363ff8944e17d94fea79767b6bed Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 6 Jul 2016 10:01:23 -0700
Subject: Rename "Chisel" to "chisel3" (only git mv).

---
 .../src/main/scala/chisel3/core/Data.scala         | 161 +++++++++++++++++++++
 1 file changed, 161 insertions(+)
 create mode 100644 chiselFrontend/src/main/scala/chisel3/core/Data.scala

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
new file mode 100644
index 00000000..d16843f7
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -0,0 +1,161 @@
+// See LICENSE for license details.
+
+package Chisel
+
+import scala.language.experimental.macros
+
+import internal._
+import internal.Builder.pushCommand
+import internal.firrtl._
+import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
+
+sealed abstract class Direction(name: String) {
+  override def toString: String = name
+  def flip: Direction
+}
+object INPUT  extends Direction("input") { override def flip: Direction = OUTPUT }
+object OUTPUT extends Direction("output") { override def flip: Direction = INPUT }
+object NO_DIR extends Direction("?") { override def flip: Direction = NO_DIR }
+
+@deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3")
+object debug {  // scalastyle:ignore object.name
+  def apply (arg: Data): Data = arg
+}
+
+/** Mixing in this trait flips the direction of an Aggregate. */
+trait Flipped extends Data {
+  this.overrideDirection(_.flip, !_)
+}
+
+/** This forms the root of the type system for wire data types. The data value
+  * must be representable as some number (need not be known at Chisel compile
+  * time) of bits, and must have methods to pack / unpack structured data to /
+  * from bits.
+  */
+abstract class Data(dirArg: Direction) extends HasId {
+  def dir: Direction = dirVar
+
+  // Sucks this is mutable state, but cloneType doesn't take a Direction arg
+  private var isFlipVar = dirArg == INPUT
+  private var dirVar = dirArg
+  private[Chisel] def isFlip = isFlipVar
+
+  private[Chisel] def overrideDirection(newDir: Direction => Direction,
+                                        newFlip: Boolean => Boolean): this.type = {
+    this.isFlipVar = newFlip(this.isFlipVar)
+    for (field <- this.flatten)
+      (field: Data).dirVar = newDir((field: Data).dirVar)
+    this
+  }
+  def asInput: this.type = cloneType.overrideDirection(_ => INPUT, _ => true)
+  def asOutput: this.type = cloneType.overrideDirection(_ => OUTPUT, _ => false)
+  def flip(): this.type = cloneType.overrideDirection(_.flip, !_)
+
+  private[Chisel] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+    throwException(s"cannot connect ${this} and ${that}")
+  private[Chisel] def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+    pushCommand(Connect(sourceInfo, this.lref, that.ref))
+  private[Chisel] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+    pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))
+  private[Chisel] def lref: Node = Node(this)
+  private[Chisel] def ref: Arg = if (isLit) litArg.get else lref
+  private[Chisel] def cloneTypeWidth(width: Width): this.type
+  private[Chisel] def toType: String
+
+  def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this badConnect that
+
+  def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = this badConnect that
+
+  def cloneType: this.type
+  def litArg(): Option[LitArg] = None
+  def litValue(): BigInt = litArg.get.num
+  def isLit(): Boolean = litArg.isDefined
+
+  def width: Width
+  final def getWidth: Int = width.get
+
+  // While this being in the Data API doesn't really make sense (should be in
+  // Aggregate, right?) this is because of an implementation limitation:
+  // cloneWithDirection, which is private and defined here, needs flatten to
+  // set element directionality.
+  // Related: directionality is mutable state. A possible solution for both is
+  // to define directionality relative to the container, but these parent links
+  // currently don't exist (while this information may be available during
+  // FIRRTL emission, it would break directionality querying from Chisel, which
+  // does get used).
+  private[Chisel] def flatten: IndexedSeq[Bits]
+
+  /** Creates an new instance of this type, unpacking the input Bits into
+    * structured data.
+    *
+    * This performs the inverse operation of toBits.
+    *
+    * @note does NOT assign to the object this is called on, instead creates
+    * and returns a NEW object (useful in a clone-and-assign scenario)
+    * @note does NOT check bit widths, may drop bits during assignment
+    * @note what fromBits assigs to must have known widths
+    */
+  def fromBits(that: Bits): this.type = macro SourceInfoTransform.thatArg
+
+  def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo): this.type = {
+    var i = 0
+    val wire = Wire(this.cloneType)
+    val bits =
+      if (that.width.known && that.width.get >= wire.width.get) {
+        that
+      } else {
+        Wire(that.cloneTypeWidth(wire.width), init = that)
+      }
+    for (x <- wire.flatten) {
+      x := bits(i + x.getWidth-1, i)
+      i += x.getWidth
+    }
+    wire.asInstanceOf[this.type]
+  }
+
+  /** Packs the value of this object as plain Bits.
+    *
+    * This performs the inverse operation of fromBits(Bits).
+    */
+  @deprecated("Use asBits, which makes the reinterpret cast more explicit and actually returns Bits", "chisel3")
+  def toBits(): UInt = SeqUtils.do_asUInt(this.flatten)(DeprecatedSourceInfo)
+}
+
+object Wire {
+  def apply[T <: Data](t: T): T = macro WireTransform.apply[T]
+
+  // No source info since Scala macros don't yet support named / default arguments.
+  def apply[T <: Data](dummy: Int = 0, init: T): T =
+    do_apply(null.asInstanceOf[T], init)(UnlocatableSourceInfo)
+
+  // No source info since Scala macros don't yet support named / default arguments.
+  def apply[T <: Data](t: T, init: T): T =
+    do_apply(t, init)(UnlocatableSourceInfo)
+
+  def do_apply[T <: Data](t: T, init: T)(implicit sourceInfo: SourceInfo): T = {
+    val x = Reg.makeType(t, null.asInstanceOf[T], init)
+    pushCommand(DefWire(sourceInfo, x))
+    pushCommand(DefInvalid(sourceInfo, x.ref))
+    if (init != null) {
+      x := init
+    }
+    x
+  }
+}
+
+object Clock {
+  def apply(dir: Direction = NO_DIR): Clock = new Clock(dir)
+}
+
+// TODO: Document this.
+sealed class Clock(dirArg: Direction) extends Element(dirArg, Width(1)) {
+  def cloneType: this.type = Clock(dirArg).asInstanceOf[this.type]
+  private[Chisel] override def flatten: IndexedSeq[Bits] = IndexedSeq()
+  private[Chisel] def cloneTypeWidth(width: Width): this.type = cloneType
+  private[Chisel] def toType = "Clock"
+
+  override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
+    case _: Clock => this connect that
+    case _ => this badConnect that
+  }
+}
-- 
cgit v1.2.3


From 12810b5efe6a8f872fbc1c63cdfb835ca354624f Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 6 Jul 2016 09:31:47 -0700
Subject: Update Chisel -> chisel3 references.

---
 .../src/main/scala/chisel3/core/Data.scala         | 38 +++++++++++-----------
 1 file changed, 19 insertions(+), 19 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index d16843f7..fcdc86bb 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -1,13 +1,13 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
 
 sealed abstract class Direction(name: String) {
   override def toString: String = name
@@ -38,9 +38,9 @@ abstract class Data(dirArg: Direction) extends HasId {
   // Sucks this is mutable state, but cloneType doesn't take a Direction arg
   private var isFlipVar = dirArg == INPUT
   private var dirVar = dirArg
-  private[Chisel] def isFlip = isFlipVar
+  private[core] def isFlip = isFlipVar
 
-  private[Chisel] def overrideDirection(newDir: Direction => Direction,
+  private[core] def overrideDirection(newDir: Direction => Direction,
                                         newFlip: Boolean => Boolean): this.type = {
     this.isFlipVar = newFlip(this.isFlipVar)
     for (field <- this.flatten)
@@ -51,16 +51,16 @@ abstract class Data(dirArg: Direction) extends HasId {
   def asOutput: this.type = cloneType.overrideDirection(_ => OUTPUT, _ => false)
   def flip(): this.type = cloneType.overrideDirection(_.flip, !_)
 
-  private[Chisel] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+  private[core] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     throwException(s"cannot connect ${this} and ${that}")
-  private[Chisel] def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+  private[core] def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     pushCommand(Connect(sourceInfo, this.lref, that.ref))
-  private[Chisel] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+  private[core] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))
-  private[Chisel] def lref: Node = Node(this)
-  private[Chisel] def ref: Arg = if (isLit) litArg.get else lref
-  private[Chisel] def cloneTypeWidth(width: Width): this.type
-  private[Chisel] def toType: String
+  private[core] def lref: Node = Node(this)
+  private[chisel3] def ref: Arg = if (isLit) litArg.get else lref
+  private[core] def cloneTypeWidth(width: Width): this.type
+  private[chisel3] def toType: String
 
   def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this badConnect that
 
@@ -71,7 +71,7 @@ abstract class Data(dirArg: Direction) extends HasId {
   def litValue(): BigInt = litArg.get.num
   def isLit(): Boolean = litArg.isDefined
 
-  def width: Width
+  private[core] def width: Width
   final def getWidth: Int = width.get
 
   // While this being in the Data API doesn't really make sense (should be in
@@ -83,7 +83,7 @@ abstract class Data(dirArg: Direction) extends HasId {
   // currently don't exist (while this information may be available during
   // FIRRTL emission, it would break directionality querying from Chisel, which
   // does get used).
-  private[Chisel] def flatten: IndexedSeq[Bits]
+  private[chisel3] def flatten: IndexedSeq[Bits]
 
   /** Creates an new instance of this type, unpacking the input Bits into
     * structured data.
@@ -150,9 +150,9 @@ object Clock {
 // TODO: Document this.
 sealed class Clock(dirArg: Direction) extends Element(dirArg, Width(1)) {
   def cloneType: this.type = Clock(dirArg).asInstanceOf[this.type]
-  private[Chisel] override def flatten: IndexedSeq[Bits] = IndexedSeq()
-  private[Chisel] def cloneTypeWidth(width: Width): this.type = cloneType
-  private[Chisel] def toType = "Clock"
+  private[chisel3] override def flatten: IndexedSeq[Bits] = IndexedSeq()
+  private[core] def cloneTypeWidth(width: Width): this.type = cloneType
+  private[chisel3] def toType = "Clock"
 
   override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
     case _: Clock => this connect that
-- 
cgit v1.2.3


From 3120eefc8a73b5ab3d8f909445a3e004b5e60cc6 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 19 Jul 2016 15:08:22 -0700
Subject: Incorporate connection logic. Compiles but fails tests.

---
 .../src/main/scala/chisel3/core/Data.scala         | 143 +++++++++++++++------
 1 file changed, 102 insertions(+), 41 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index fcdc86bb..4cc66cb5 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -13,18 +13,69 @@ sealed abstract class Direction(name: String) {
   override def toString: String = name
   def flip: Direction
 }
-object INPUT  extends Direction("input") { override def flip: Direction = OUTPUT }
-object OUTPUT extends Direction("output") { override def flip: Direction = INPUT }
-object NO_DIR extends Direction("?") { override def flip: Direction = NO_DIR }
+object Direction {
+  object Input  extends Direction("input") { override def flip: Direction = Output }
+  object Output extends Direction("output") { override def flip: Direction = Input }
+}
 
 @deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3")
 object debug {  // scalastyle:ignore object.name
   def apply (arg: Data): Data = arg
 }
 
-/** Mixing in this trait flips the direction of an Aggregate. */
-trait Flipped extends Data {
-  this.overrideDirection(_.flip, !_)
+object DataMirror {
+  def widthOf(target: Data): Width = target.width
+}
+
+/**
+* Input, Output, and Flipped are used to define the directions of Module IOs.
+*
+* Note that they do not currently call target to be a newType or cloneType.
+* This is nominally for performance reasons to avoid too many extra copies when
+* something is flipped multiple times.
+*
+* Thus, an error will be thrown if these are used on bound Data
+*/
+object Input {
+  def apply[T<:Data](target: T): T =
+    Binding.bind(target, InputBinder, "Error: Cannot set as input ")
+}
+object Output {
+  def apply[T<:Data](target: T): T =
+    Binding.bind(target, OutputBinder, "Error: Cannot set as output ")
+}
+object Flipped {
+  def apply[T<:Data](target: T): T =
+    Binding.bind(target, FlippedBinder, "Error: Cannot flip ")
+}
+
+object Data {
+  /**
+  * This function returns true if the FIRRTL type of this Data should be flipped
+  * relative to other nodes.
+  *
+  * Note that the current scheme only applies Flip to Elements or Vec chains of
+  * Elements.
+  *
+  * A Bundle is never marked flip, instead preferring its root fields to be marked
+  *
+  * The Vec check is due to the fact that flip must be factored out of the vec, ie:
+  * must have flip field: Vec(UInt) instead of field: Vec(flip UInt)
+  */
+  private[chisel3] def isFlipped(target: Data): Boolean = target match {
+    case (element: Element) => element.binding.direction == Some(Direction.Input)
+    case (vec: Vec[Data @unchecked]) => isFlipped(vec.sample_element)
+    case (bundle: Bundle) => false
+  }
+
+  implicit class AddDirectionToData[T<:Data](val target: T) extends AnyVal {
+    @deprecated("Input(Data) should be used over Data.asInput", "gchisel")
+    def asInput: T = Input(target)
+    @deprecated("Output(Data) should be used over Data.asOutput", "gchisel")
+    def asOutput: T = Output(target)
+    @deprecated("Flipped(Data) should be used over Data.flip", "gchisel")
+    def flip(): T = Flipped(target)
+  }
 }
 
 /** This forms the root of the type system for wire data types. The data value
@@ -32,41 +83,45 @@ trait Flipped extends Data {
   * time) of bits, and must have methods to pack / unpack structured data to /
   * from bits.
   */
-abstract class Data(dirArg: Direction) extends HasId {
-  def dir: Direction = dirVar
-
-  // Sucks this is mutable state, but cloneType doesn't take a Direction arg
-  private var isFlipVar = dirArg == INPUT
-  private var dirVar = dirArg
-  private[core] def isFlip = isFlipVar
-
-  private[core] def overrideDirection(newDir: Direction => Direction,
-                                        newFlip: Boolean => Boolean): this.type = {
-    this.isFlipVar = newFlip(this.isFlipVar)
-    for (field <- this.flatten)
-      (field: Data).dirVar = newDir((field: Data).dirVar)
-    this
-  }
-  def asInput: this.type = cloneType.overrideDirection(_ => INPUT, _ => true)
-  def asOutput: this.type = cloneType.overrideDirection(_ => OUTPUT, _ => false)
-  def flip(): this.type = cloneType.overrideDirection(_.flip, !_)
+abstract class Data extends HasId {
+  // Return ALL elements at root of this type.
+  // Contasts with flatten, which returns just Bits
+  private[chisel3] def allElements: Seq[Element]
 
   private[core] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     throwException(s"cannot connect ${this} and ${that}")
-  private[core] def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
-    pushCommand(Connect(sourceInfo, this.lref, that.ref))
-  private[core] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
-    pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))
-  private[core] def lref: Node = Node(this)
+  private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit = {
+    Binding.checkSynthesizable(this, s"'this' ($this)")
+    Binding.checkSynthesizable(that, s"'that' ($that)")
+    try {
+      MonoConnect.connect(sourceInfo, this, that, Builder.forcedModule)
+    } catch {
+      case MonoConnect.MonoConnectException(message) =>
+        throwException(
+          s"Connection between sink ($this) and source ($that) failed @$message"
+        )
+    }
+  }
+  private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit = {
+    Binding.checkSynthesizable(this, s"'this' ($this)")
+    Binding.checkSynthesizable(that, s"'that' ($that)")
+    try {
+      BiConnect.connect(sourceInfo, this, that, Builder.forcedModule)
+    } catch {
+      case BiConnect.BiConnectException(message) =>
+        throwException(
+          s"Connection between left ($this) and source ($that) failed @$message"
+        )
+    }
+  }
+  private[chisel3] def lref: Node = Node(this)
   private[chisel3] def ref: Arg = if (isLit) litArg.get else lref
-  private[core] def cloneTypeWidth(width: Width): this.type
+  private[chisel3] def cloneTypeWidth(width: Width): this.type
   private[chisel3] def toType: String
 
-  def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this badConnect that
-
-  def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = this badConnect that
-
   def cloneType: this.type
+  final def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this connect that
+  final def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = this bulkConnect that
   def litArg(): Option[LitArg] = None
   def litValue(): BigInt = litArg.get.num
   def isLit(): Boolean = litArg.isDefined
@@ -134,28 +189,34 @@ object Wire {
 
   def do_apply[T <: Data](t: T, init: T)(implicit sourceInfo: SourceInfo): T = {
     val x = Reg.makeType(t, null.asInstanceOf[T], init)
+
+    // Bind each element of x to being a Wire
+    Binding.bind(x, WireBinder(Builder.forcedModule), "Error: t")
+
     pushCommand(DefWire(sourceInfo, x))
     pushCommand(DefInvalid(sourceInfo, x.ref))
     if (init != null) {
+      Binding.checkSynthesizable(init, s"'init' ($init)")
       x := init
     }
+
     x
   }
 }
 
 object Clock {
-  def apply(dir: Direction = NO_DIR): Clock = new Clock(dir)
+  def apply(): Clock = new Clock
 }
 
 // TODO: Document this.
-sealed class Clock(dirArg: Direction) extends Element(dirArg, Width(1)) {
-  def cloneType: this.type = Clock(dirArg).asInstanceOf[this.type]
+sealed class Clock extends Element(Width(1)) {
+  def cloneType: this.type = Clock().asInstanceOf[this.type]
   private[chisel3] override def flatten: IndexedSeq[Bits] = IndexedSeq()
-  private[core] def cloneTypeWidth(width: Width): this.type = cloneType
+  private[chisel3] def cloneTypeWidth(width: Width): this.type = cloneType
   private[chisel3] def toType = "Clock"
 
-  override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
-    case _: Clock => this connect that
-    case _ => this badConnect that
+  override def connect (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
+    case _: Clock => super.connect(that)(sourceInfo)
+    case _ => super.badConnect(that)(sourceInfo)
   }
 }
-- 
cgit v1.2.3


From 28e80311f172ae4d1d477e8bb47ca3719c9a8fc5 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 20 Jul 2016 13:28:15 -0700
Subject: Compile ok. Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x)

---
 chiselFrontend/src/main/scala/chisel3/core/Data.scala | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 4cc66cb5..79119114 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -174,6 +174,13 @@ abstract class Data extends HasId {
     */
   @deprecated("Use asBits, which makes the reinterpret cast more explicit and actually returns Bits", "chisel3")
   def toBits(): UInt = SeqUtils.do_asUInt(this.flatten)(DeprecatedSourceInfo)
+
+  protected def unBind(): Unit = {
+    //TODO(twigg): Do recursively for better error messages
+    for(elem <- this.allElements) {
+      elem.binding = UnboundBinding(elem.binding.direction)
+    }
+  }
 }
 
 object Wire {
@@ -210,7 +217,11 @@ object Clock {
 
 // TODO: Document this.
 sealed class Clock extends Element(Width(1)) {
-  def cloneType: this.type = Clock().asInstanceOf[this.type]
+  def cloneType: this.type = {
+    val clone = Clock().asInstanceOf[this.type]
+    clone.unBind()
+    clone
+  }
   private[chisel3] override def flatten: IndexedSeq[Bits] = IndexedSeq()
   private[chisel3] def cloneTypeWidth(width: Width): this.type = cloneType
   private[chisel3] def toType = "Clock"
-- 
cgit v1.2.3


From 7c9043859994b32bb07d2fce4ae61a7a3362a1b3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 21 Jul 2016 17:12:06 -0700
Subject: Introduce chiselCloneType to distinguish from cloneType. Still fails
 one test - DirectionSpec in Direction.scala

---
 .../src/main/scala/chisel3/core/Data.scala         | 24 ++++++++++------------
 1 file changed, 11 insertions(+), 13 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 79119114..fee5c01c 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -120,6 +120,15 @@ abstract class Data extends HasId {
   private[chisel3] def toType: String
 
   def cloneType: this.type
+  def chiselCloneType: this.type = {
+    // Call the user-supplied cloneType method
+    val clone = this.cloneType
+    //TODO(twigg): Do recursively for better error messages
+    for((clone_elem, source_elem) <- clone.allElements zip this.allElements) {
+      clone_elem.binding = UnboundBinding(source_elem.binding.direction)
+    }
+    clone
+  }
   final def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this connect that
   final def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = this bulkConnect that
   def litArg(): Option[LitArg] = None
@@ -154,7 +163,7 @@ abstract class Data extends HasId {
 
   def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo): this.type = {
     var i = 0
-    val wire = Wire(this.cloneType)
+    val wire = Wire(this.chiselCloneType)
     val bits =
       if (that.width.known && that.width.get >= wire.width.get) {
         that
@@ -174,13 +183,6 @@ abstract class Data extends HasId {
     */
   @deprecated("Use asBits, which makes the reinterpret cast more explicit and actually returns Bits", "chisel3")
   def toBits(): UInt = SeqUtils.do_asUInt(this.flatten)(DeprecatedSourceInfo)
-
-  protected def unBind(): Unit = {
-    //TODO(twigg): Do recursively for better error messages
-    for(elem <- this.allElements) {
-      elem.binding = UnboundBinding(elem.binding.direction)
-    }
-  }
 }
 
 object Wire {
@@ -217,11 +219,7 @@ object Clock {
 
 // TODO: Document this.
 sealed class Clock extends Element(Width(1)) {
-  def cloneType: this.type = {
-    val clone = Clock().asInstanceOf[this.type]
-    clone.unBind()
-    clone
-  }
+  def cloneType: this.type = Clock().asInstanceOf[this.type]
   private[chisel3] override def flatten: IndexedSeq[Bits] = IndexedSeq()
   private[chisel3] def cloneTypeWidth(width: Width): this.type = cloneType
   private[chisel3] def toType = "Clock"
-- 
cgit v1.2.3


From e09a09e3f4e5d6d8650b1db4add96c0a5b09e8ca Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 25 Jul 2016 16:36:06 -0700
Subject: Enable current (chisel2-style) compatibility mode.

---
 chiselFrontend/src/main/scala/chisel3/core/Data.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 9e362fa6..73470383 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -16,6 +16,7 @@ sealed abstract class Direction(name: String) {
 object Direction {
   object Input  extends Direction("input") { override def flip: Direction = Output }
   object Output extends Direction("output") { override def flip: Direction = Input }
+  object Unspecified extends Direction("unspecified") { override def flip: Direction = Unspecified }
 }
 
 @deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3")
-- 
cgit v1.2.3


From 8e24085e112d595cfaf2dc7d54bce974498521d5 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 4 Aug 2016 13:40:35 -0700
Subject: Deal with directions on Clocks.

---
 chiselFrontend/src/main/scala/chisel3/core/Data.scala | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 8c874070..9115d1ba 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -227,6 +227,14 @@ object Wire {
 
 object Clock {
   def apply(): Clock = new Clock
+  def apply(dir: Direction): Clock = {
+    val result = apply()
+    dir match {
+      case Direction.Input => Input(result)
+      case Direction.Output => Output(result)
+      case Direction.Unspecified => result
+    }
+  }
 }
 
 // TODO: Document this.
-- 
cgit v1.2.3


From 525e5688f69f474240fe5a21d6210beb04cfef29 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Fri, 19 Aug 2016 14:46:53 -0700
Subject: Restore immutability of direction overrides. Input, Output, and
 Flipped clone their inputs.

---
 chiselFrontend/src/main/scala/chisel3/core/Data.scala | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index cb6d427d..ce7b58b4 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -31,27 +31,28 @@ object DataMirror {
 /**
 * Input, Output, and Flipped are used to define the directions of Module IOs.
 *
-* Note that they do not currently call target to be a newType or cloneType.
-* This is nominally for performance reasons to avoid too many extra copies when
-* something is flipped multiple times.
+* Note that they currently clone their source argument, including its bindings.
 *
 * Thus, an error will be thrown if these are used on bound Data
 */
 object Input {
-  def apply[T<:Data](target: T): T = {
+  def apply[T<:Data](source: T): T = {
+    val target = source.chiselCloneType
     Data.setFirrtlDirection(target, Direction.Input)
     Binding.bind(target, InputBinder, "Error: Cannot set as input ")
   }
 }
 object Output {
-  def apply[T<:Data](target: T): T = {
+  def apply[T<:Data](source: T): T = {
+    val target = source.chiselCloneType
     Data.setFirrtlDirection(target, Direction.Output)
     Binding.bind(target, OutputBinder, "Error: Cannot set as output ")
   }
 }
 object Flipped {
-  def apply[T<:Data](target: T): T = {
-    Data.setFirrtlDirection(target, Data.getFirrtlDirection(target).flip)
+  def apply[T<:Data](source: T): T = {
+    val target = source.chiselCloneType
+    Data.setFirrtlDirection(target, Data.getFirrtlDirection(source).flip)
     Binding.bind(target, FlippedBinder, "Error: Cannot flip ")
   }
 }
-- 
cgit v1.2.3


From 4b88a5dd45337fa88178fe17324eef3661daf1b3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 1 Sep 2016 10:21:57 -0700
Subject: Move connection implicits from Module constructor to connection
 methods. Eliminate builder compileOptions.

---
 chiselFrontend/src/main/scala/chisel3/core/Data.scala | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index ce7b58b4..bda06790 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -8,6 +8,7 @@ import chisel3.internal._
 import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl._
 import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
+import chisel3.Strict.CompileOptions
 
 sealed abstract class Direction(name: String) {
   override def toString: String = name
@@ -124,11 +125,11 @@ abstract class Data extends HasId {
 
   private[core] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     throwException(s"cannot connect ${this} and ${that}")
-  private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit = {
+  private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ExplicitCompileOptions): Unit = {
     Binding.checkSynthesizable(this, s"'this' ($this)")
     Binding.checkSynthesizable(that, s"'that' ($that)")
     try {
-      MonoConnect.connect(sourceInfo, this, that, Builder.forcedModule)
+      MonoConnect.connect(sourceInfo, connectCompileOptions, this, that, Builder.forcedModule)
     } catch {
       case MonoConnect.MonoConnectException(message) =>
         throwException(
@@ -136,11 +137,11 @@ abstract class Data extends HasId {
         )
     }
   }
-  private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit = {
+  private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ExplicitCompileOptions): Unit = {
     Binding.checkSynthesizable(this, s"'this' ($this)")
     Binding.checkSynthesizable(that, s"'that' ($that)")
     try {
-      BiConnect.connect(sourceInfo, this, that, Builder.forcedModule)
+      BiConnect.connect(sourceInfo, connectCompileOptions, this, that, Builder.forcedModule)
     } catch {
       case BiConnect.BiConnectException(message) =>
         throwException(
@@ -165,8 +166,8 @@ abstract class Data extends HasId {
     }
     clone
   }
-  final def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this connect that
-  final def <> (that: Data)(implicit sourceInfo: SourceInfo): Unit = this bulkConnect that
+  final def := (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: ExplicitCompileOptions): Unit = this.connect(that)(sourceInfo, connectionCompileOptions)
+  final def <> (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: ExplicitCompileOptions): Unit = this.bulkConnect(that)(sourceInfo, connectionCompileOptions)
   def litArg(): Option[LitArg] = None
   def litValue(): BigInt = litArg.get.num
   def isLit(): Boolean = litArg.isDefined
@@ -254,7 +255,7 @@ object Wire {
     do_apply(t, init)(UnlocatableSourceInfo)
 
   def do_apply[T <: Data](t: T, init: T)(implicit sourceInfo: SourceInfo): T = {
-    val x = Reg.makeType(t, null.asInstanceOf[T], init)
+    val x = Reg.makeType(chisel3.Strict.CompileOptions, t, null.asInstanceOf[T], init)
 
     // Bind each element of x to being a Wire
     Binding.bind(x, WireBinder(Builder.forcedModule), "Error: t")
@@ -288,8 +289,8 @@ sealed class Clock extends Element(Width(1)) {
   private[core] def cloneTypeWidth(width: Width): this.type = cloneType
   private[chisel3] def toType = "Clock"
 
-  override def connect (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
-    case _: Clock => super.connect(that)(sourceInfo)
+  override def connect (that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ExplicitCompileOptions): Unit = that match {
+    case _: Clock => super.connect(that)(sourceInfo, connectCompileOptions)
     case _ => super.badConnect(that)(sourceInfo)
   }
 }
-- 
cgit v1.2.3


From 19f5b7c6841bda318288990e643eb02fa22a49e2 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Fri, 9 Sep 2016 17:23:14 -0700
Subject: Convert to NotStrict for internal connection checks.

---
 chiselFrontend/src/main/scala/chisel3/core/Data.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index bda06790..991b1898 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -8,7 +8,7 @@ import chisel3.internal._
 import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl._
 import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
-import chisel3.Strict.CompileOptions
+import chisel3.NotStrict.CompileOptions
 
 sealed abstract class Direction(name: String) {
   override def toString: String = name
@@ -255,7 +255,7 @@ object Wire {
     do_apply(t, init)(UnlocatableSourceInfo)
 
   def do_apply[T <: Data](t: T, init: T)(implicit sourceInfo: SourceInfo): T = {
-    val x = Reg.makeType(chisel3.Strict.CompileOptions, t, null.asInstanceOf[T], init)
+    val x = Reg.makeType(chisel3.NotStrict.CompileOptions, t, null.asInstanceOf[T], init)
 
     // Bind each element of x to being a Wire
     Binding.bind(x, WireBinder(Builder.forcedModule), "Error: t")
-- 
cgit v1.2.3


From 2edfe895e4ff9f751c52904f73fe701502aa926a Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 28 Sep 2016 08:43:59 -0700
Subject: Don't use firrtlDirection for direction checks - fix #298.
 firrtlDirection should only be used for emitting firrtl. Any checks on the
 actual direction should use the bound Direction `dir`.

---
 chiselFrontend/src/main/scala/chisel3/core/Data.scala | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 4bb58572..52bc8128 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -241,7 +241,9 @@ abstract class Data extends HasId {
 
   // firrtlDirection is the direction we report to firrtl.
   // It maintains the user-specified value (as opposed to the "actual" or applied/propagated value).
-  var firrtlDirection: Direction = Direction.Unspecified
+  // NOTE: This should only be used for emitting acceptable firrtl.
+  // The Element.dir should be used for any tests involving direction.
+  private var firrtlDirection: Direction = Direction.Unspecified
   /** Default pretty printing */
   def toPrintable: Printable
 }
-- 
cgit v1.2.3


From eb5e5dc30019be342b7a0534b425bf33b7984ce3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 29 Sep 2016 11:44:09 -0700
Subject: Massive rename of CompileOptions. Massage CompileOption names in an
 attempt to preserve default (Strict) CompileOptions in the absence of
 explicit imports. NOTE: Since the default is now strict, we may encounter
 errors when we generate connections for clients (i.e., in Vec.do_apply() when
 we wire up a sequence). We should really thread the CompileOptions through
 the macro system so the client's implicits are used.

---
 chiselFrontend/src/main/scala/chisel3/core/Data.scala | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 52bc8128..1b08374a 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -9,7 +9,7 @@ import chisel3.internal.Builder.{pushCommand, pushOp}
 import chisel3.internal.firrtl._
 import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
 import chisel3.internal.firrtl.PrimOp.AsUIntOp
-import chisel3.NotStrict.CompileOptions
+import chisel3.ImplicitCompileOptions
 
 sealed abstract class Direction(name: String) {
   override def toString: String = name
@@ -126,7 +126,7 @@ abstract class Data extends HasId {
 
   private[core] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     throwException(s"cannot connect ${this} and ${that}")
-  private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ExplicitCompileOptions): Unit = {
+  private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ImplicitCompileOptions): Unit = {
     Binding.checkSynthesizable(this, s"'this' ($this)")
     Binding.checkSynthesizable(that, s"'that' ($that)")
     try {
@@ -138,7 +138,7 @@ abstract class Data extends HasId {
         )
     }
   }
-  private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ExplicitCompileOptions): Unit = {
+  private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ImplicitCompileOptions): Unit = {
     Binding.checkSynthesizable(this, s"'this' ($this)")
     Binding.checkSynthesizable(that, s"'that' ($that)")
     try {
@@ -167,8 +167,8 @@ abstract class Data extends HasId {
     }
     clone
   }
-  final def := (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: ExplicitCompileOptions): Unit = this.connect(that)(sourceInfo, connectionCompileOptions)
-  final def <> (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: ExplicitCompileOptions): Unit = this.bulkConnect(that)(sourceInfo, connectionCompileOptions)
+  final def := (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: ImplicitCompileOptions): Unit = this.connect(that)(sourceInfo, connectionCompileOptions)
+  final def <> (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: ImplicitCompileOptions): Unit = this.bulkConnect(that)(sourceInfo, connectionCompileOptions)
   def litArg(): Option[LitArg] = None
   def litValue(): BigInt = litArg.get.num
   def isLit(): Boolean = litArg.isDefined
@@ -260,7 +260,7 @@ object Wire {
     do_apply(t, init)(UnlocatableSourceInfo)
 
   def do_apply[T <: Data](t: T, init: T)(implicit sourceInfo: SourceInfo): T = {
-    val x = Reg.makeType(chisel3.NotStrict.CompileOptions, t, null.asInstanceOf[T], init)
+    val x = Reg.makeType(chisel3.ExplicitCompileOptions.NotStrict, t, null.asInstanceOf[T], init)
 
     // Bind each element of x to being a Wire
     Binding.bind(x, WireBinder(Builder.forcedModule), "Error: t")
@@ -294,7 +294,7 @@ sealed class Clock extends Element(Width(1)) {
   private[core] def cloneTypeWidth(width: Width): this.type = cloneType
   private[chisel3] def toType = "Clock"
 
-  override def connect (that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ExplicitCompileOptions): Unit = that match {
+  override def connect (that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ImplicitCompileOptions): Unit = that match {
     case _: Clock => super.connect(that)(sourceInfo, connectCompileOptions)
     case _ => super.badConnect(that)(sourceInfo)
   }
-- 
cgit v1.2.3


From 96fb6a5e2c781b20470d02eac186b1b129c20bdf Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 29 Sep 2016 14:57:42 -0700
Subject: Consolidate CompileOptions and re-enable NotStrict pending macro
 work.

---
 chiselFrontend/src/main/scala/chisel3/core/Data.scala | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 1b08374a..83619fc8 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -9,7 +9,7 @@ import chisel3.internal.Builder.{pushCommand, pushOp}
 import chisel3.internal.firrtl._
 import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
 import chisel3.internal.firrtl.PrimOp.AsUIntOp
-import chisel3.ImplicitCompileOptions
+//import chisel3.CompileOptions
 
 sealed abstract class Direction(name: String) {
   override def toString: String = name
@@ -126,7 +126,7 @@ abstract class Data extends HasId {
 
   private[core] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     throwException(s"cannot connect ${this} and ${that}")
-  private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ImplicitCompileOptions): Unit = {
+  private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = {
     Binding.checkSynthesizable(this, s"'this' ($this)")
     Binding.checkSynthesizable(that, s"'that' ($that)")
     try {
@@ -138,7 +138,7 @@ abstract class Data extends HasId {
         )
     }
   }
-  private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ImplicitCompileOptions): Unit = {
+  private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = {
     Binding.checkSynthesizable(this, s"'this' ($this)")
     Binding.checkSynthesizable(that, s"'that' ($that)")
     try {
@@ -167,8 +167,8 @@ abstract class Data extends HasId {
     }
     clone
   }
-  final def := (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: ImplicitCompileOptions): Unit = this.connect(that)(sourceInfo, connectionCompileOptions)
-  final def <> (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: ImplicitCompileOptions): Unit = this.bulkConnect(that)(sourceInfo, connectionCompileOptions)
+  final def := (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.connect(that)(sourceInfo, connectionCompileOptions)
+  final def <> (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.bulkConnect(that)(sourceInfo, connectionCompileOptions)
   def litArg(): Option[LitArg] = None
   def litValue(): BigInt = litArg.get.num
   def isLit(): Boolean = litArg.isDefined
@@ -260,7 +260,7 @@ object Wire {
     do_apply(t, init)(UnlocatableSourceInfo)
 
   def do_apply[T <: Data](t: T, init: T)(implicit sourceInfo: SourceInfo): T = {
-    val x = Reg.makeType(chisel3.ExplicitCompileOptions.NotStrict, t, null.asInstanceOf[T], init)
+    val x = Reg.makeType(chisel3.core.ExplicitCompileOptions.NotStrict, t, null.asInstanceOf[T], init)
 
     // Bind each element of x to being a Wire
     Binding.bind(x, WireBinder(Builder.forcedModule), "Error: t")
@@ -294,7 +294,7 @@ sealed class Clock extends Element(Width(1)) {
   private[core] def cloneTypeWidth(width: Width): this.type = cloneType
   private[chisel3] def toType = "Clock"
 
-  override def connect (that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: ImplicitCompileOptions): Unit = that match {
+  override def connect (that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = that match {
     case _: Clock => super.connect(that)(sourceInfo, connectCompileOptions)
     case _ => super.badConnect(that)(sourceInfo)
   }
-- 
cgit v1.2.3


From 398edafd809c3abda751432c51a07b6b1158ecbd Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 29 Sep 2016 15:43:34 -0700
Subject: Manual dead code elimination.

---
 chiselFrontend/src/main/scala/chisel3/core/Data.scala | 1 -
 1 file changed, 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 83619fc8..3f21a34c 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -9,7 +9,6 @@ import chisel3.internal.Builder.{pushCommand, pushOp}
 import chisel3.internal.firrtl._
 import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
 import chisel3.internal.firrtl.PrimOp.AsUIntOp
-//import chisel3.CompileOptions
 
 sealed abstract class Direction(name: String) {
   override def toString: String = name
-- 
cgit v1.2.3