Merge pull request #315 from ucb-bar/fix-rocket-chip

Give <> and := legacy behavior in compatibility mode

1 files changed, 4 insertions, 0 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala b/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala
index 85aa8cdc..4dea39b5 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala
@@ -20,6 +20,8 @@ trait CompileOptions {
   // Issue a deprecation warning if Data.{flip, asInput,asOutput} is used
   // instead of Flipped, Input, or Output.
   val deprecateOldDirectionMethods: Boolean
+  // Check that referenced Data have actually been declared.
+  val checkSynthesizable: Boolean
 }
 
 object CompileOptions {
@@ -38,6 +40,7 @@ object ExplicitCompileOptions {
     val dontTryConnectionsSwapped = false
     val dontAssumeDirectionality = false
     val deprecateOldDirectionMethods = false
+    val checkSynthesizable = false
   }
 
   // Collection of "strict" connection compile options, preferred for new code.
@@ -49,5 +52,6 @@ object ExplicitCompileOptions {
     val dontTryConnectionsSwapped = true
     val dontAssumeDirectionality = true
     val deprecateOldDirectionMethods = true
+    val checkSynthesizable = true
   }
 }