diff options
| author | Richard Lin | 2016-09-29 15:37:44 -0700 |
|---|---|---|
| committer | GitHub | 2016-09-29 15:37:44 -0700 |
| commit | 3368a032d7c8ef1022bd9330ef4c4931367ba46b (patch) | |
| tree | 242e9c5d1c5e63bb73bb3cb2c11d056a9e3bbcb9 /chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala | |
| parent | 12a651513541d6c96e3b709b424d5d3384179076 (diff) | |
| parent | 96fb6a5e2c781b20470d02eac186b1b129c20bdf (diff) | |
Merge pull request #302 from ucb-bar/gsdt-renamecompileoptions
Massive rename of CompileOptions.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala index 7b0cf3f7..c1352566 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala @@ -5,7 +5,8 @@ package chisel3.core import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl.{ModuleIO, DefInvalid} import chisel3.internal.sourceinfo.SourceInfo -import chisel3.NotStrict.CompileOptions +// TODO: remove this once we have CompileOptions threaded through the macro system. +import chisel3.core.ExplicitCompileOptions.NotStrict /** Defines a black box, which is a module that can be referenced from within * Chisel, but is not defined in the emitted Verilog. Useful for connecting |