From eb5e5dc30019be342b7a0534b425bf33b7984ce3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 29 Sep 2016 11:44:09 -0700
Subject: Massive rename of CompileOptions. Massage CompileOption names in an
 attempt to preserve default (Strict) CompileOptions in the absence of
 explicit imports. NOTE: Since the default is now strict, we may encounter
 errors when we generate connections for clients (i.e., in Vec.do_apply() when
 we wire up a sequence). We should really thread the CompileOptions through
 the macro system so the client's implicits are used.

---
 chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
index 7b0cf3f7..7e61ec72 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
@@ -5,7 +5,7 @@ package chisel3.core
 import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl.{ModuleIO, DefInvalid}
 import chisel3.internal.sourceinfo.SourceInfo
-import chisel3.NotStrict.CompileOptions
+//import chisel3.ExplicitCompileOptions.NotStrict
 
 /** Defines a black box, which is a module that can be referenced from within
   * Chisel, but is not defined in the emitted Verilog. Useful for connecting
-- 
cgit v1.2.3


From 96fb6a5e2c781b20470d02eac186b1b129c20bdf Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 29 Sep 2016 14:57:42 -0700
Subject: Consolidate CompileOptions and re-enable NotStrict pending macro
 work.

---
 chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
index 7e61ec72..c1352566 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
@@ -5,7 +5,8 @@ package chisel3.core
 import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl.{ModuleIO, DefInvalid}
 import chisel3.internal.sourceinfo.SourceInfo
-//import chisel3.ExplicitCompileOptions.NotStrict
+// TODO: remove this once we have CompileOptions threaded through the macro system.
+import chisel3.core.ExplicitCompileOptions.NotStrict
 
 /** Defines a black box, which is a module that can be referenced from within
   * Chisel, but is not defined in the emitted Verilog. Useful for connecting
-- 
cgit v1.2.3