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authorRichard Lin2019-01-21 16:24:43 -0800
committerGitHub2019-01-21 16:24:43 -0800
commit9e992816e570284193e121cd9c24503fd8cb4427 (patch)
tree90205ab0c936d50f4853bb7dc6293a4b62d47edf /chiselFrontend/src/main/scala/chisel3/core/Binding.scala
parent3b3405e8bd496749dcb47e17156c0224a6f8a496 (diff)
Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) Module class names (#994)
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Binding.scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Binding.scala8
1 files changed, 4 insertions, 4 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
index 60235477..4c352bc6 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
@@ -96,11 +96,11 @@ sealed trait ReadOnlyBinding extends TopBinding
// TODO(twigg): Ops between unenclosed nodes can also be unenclosed
// However, Chisel currently binds all op results to a module
-case class OpBinding(enclosure: UserModule) extends ConstrainedBinding with ReadOnlyBinding
-case class MemoryPortBinding(enclosure: UserModule) extends ConstrainedBinding
+case class OpBinding(enclosure: RawModule) extends ConstrainedBinding with ReadOnlyBinding
+case class MemoryPortBinding(enclosure: RawModule) extends ConstrainedBinding
case class PortBinding(enclosure: BaseModule) extends ConstrainedBinding
-case class RegBinding(enclosure: UserModule) extends ConstrainedBinding
-case class WireBinding(enclosure: UserModule) extends ConstrainedBinding
+case class RegBinding(enclosure: RawModule) extends ConstrainedBinding
+case class WireBinding(enclosure: RawModule) extends ConstrainedBinding
case class ChildBinding(parent: Data) extends Binding {
def location = parent.topBinding.location