Repackagecore rebase (#1078)

* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
 and deal with the subsequent fallout.

* Move Aggregate, Clock, Mem, Printf, Reg

* Move almost all chisel3.core definitions to chisel3 or chisel3.experimental

* Revive core package object to provide aliases for moved definitions.

* Cleanup package definitions; eliminate ambiguous implicits

* Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.

* Put BitPat back in chisel3.util

* More experimental motion - avoid multiple import definitions.

* Add experimental.FixedPoint alias

* Add EnumType definition to core package.
Update deprecated messages to refer to correct object

* Move FixedPoint into the experimental package (but keep it in Bits.scala).

* Add missing implicits to core/package - compatibility

* Cleanup: update ScalaDoc references; remove unused imports

* Add Reset alias to core/package

* Use common 3.2 version in deprecation warning

* Move Binding from core to internal.

* Optimize imports.

* Repair IntelliJ's overly cleanliness.

* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
 and deal with the subsequent fallout.

Move Aggregate, Clock, Mem, Printf, Reg

Move almost all chisel3.core definitions to chisel3 or chisel3.experimental

Revive core package object to provide aliases for moved definitions.

Cleanup package definitions; eliminate ambiguous implicits

Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.

Add EnumType definition to core package.
Update deprecated messages to refer to correct object

Move FixedPoint into the experimental package (but keep it in Bits.scala).

Add missing implicits to core/package - compatibility

Cleanup: update ScalaDoc references; remove unused imports

Use common 3.2 version in deprecation warning

Move Binding from core to internal.

* Change == to reference equality (eq) in Data print (#1044)

* Remove @chiselName from MixedVec (#1045)

* Fix enum annotations (#936)

* Turned off strong enum annotations because they weren't working with Vec
indexes
* Add new EnumVecAnnotation for vecs of enums and vecs of bundles with
enum fields
* Changed Clock's width parameter back to a fixed constant value of 1
* Fixed enum annotations for Vecs of Bundles which contain enum elements
* Fixed usage of "when/otherwise" to use consistent style

* Add Record to type hierarchy documentation

* Undeprecate isLit (#1048)

* move doNotDedup to experimental (#1008)

* Aggregate coverage - aggregate tests but not publishing (#1040)

Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml
This should finally fix #772.

* Check field referential equality in autoclonetype (#1047)

* Allow naming annotation to work outside builder context (#1051)

* Try to eliminate JVM hang due to static initialization deadlock (#1053)

* Make core.DontCare private to chisel3 (#1054)

Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object.

* Ignore empty aggregates elements when binding aggregate direction (#946)

Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction

* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates

* Detect bundle aliasing (#1050)

* Implement connectFromBits in ChiselEnum (#1052)

This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf

* Optimize imports.

* Move Analog to experimental.

* More repackage cleanup - reduce differences with master.

* Cleanup chisel3 references.

* More chisel3 reference cleanup.

* Merge cleanup.

* Remove unused import

* Bump core deprecation to 3.3

* Move DontCare back into Data.scala inside package internal

* Re-indent experimental/internal package code

* Move code back to original files - facilitate comparison with other branches

* Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.

* More master diff minimization.

* Try to eliminate JVM hang due to static initialization deadlock (#1053)

* Ignore empty aggregates elements when binding aggregate direction (#946)

Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction

* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates

* Implement connectFromBits in ChiselEnum (#1052)

This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf

* Move Analog to experimental.

More repackage cleanup - reduce differences with master.

Cleanup chisel3 references.

More chisel3 reference cleanup.

* Fix wrong directionality for Vec(Flipped())

Create Chisel IR Port() in a way that Converter is happy with.
Also add more extensive test suite for future-proofing.

Close #1063

* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
 and deal with the subsequent fallout.

Move Aggregate, Clock, Mem, Printf, Reg

Move almost all chisel3.core definitions to chisel3 or chisel3.experimental

Revive core package object to provide aliases for moved definitions.

Cleanup package definitions; eliminate ambiguous implicits

Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.

Put BitPat back in chisel3.util

More experimental motion - avoid multiple import definitions.

Add experimental.FixedPoint alias

Add EnumType definition to core package.
Update deprecated messages to refer to correct object

Move FixedPoint into the experimental package (but keep it in Bits.scala).

Add missing implicits to core/package - compatibility

Cleanup: update ScalaDoc references; remove unused imports

Add Reset alias to core/package

Use common 3.2 version in deprecation warning

Move Binding from core to internal.

Optimize imports.

Repair IntelliJ's overly cleanliness.

Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
 and deal with the subsequent fallout.

Move Aggregate, Clock, Mem, Printf, Reg

Move almost all chisel3.core definitions to chisel3 or chisel3.experimental

Revive core package object to provide aliases for moved definitions.

Cleanup package definitions; eliminate ambiguous implicits

Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.

Add EnumType definition to core package.
Update deprecated messages to refer to correct object

Move FixedPoint into the experimental package (but keep it in Bits.scala).

Add missing implicits to core/package - compatibility

Cleanup: update ScalaDoc references; remove unused imports

Use common 3.2 version in deprecation warning

Move Binding from core to internal.

Optimize imports.

Merge cleanup.

Remove unused import

Bump core deprecation to 3.3

Move DontCare back into Data.scala inside package internal

Re-indent experimental/internal package code

Move code back to original files - facilitate comparison with other branches

Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.

More master diff minimization.

Fix minor discrepancies with repackagecore-testbed

* Remove redundant imports
As part of its import updating process, IntelliJ converted some import statements to `import package.{object, _}`. Is this intended to show an explicit dependency on `package.object` and a further dependency on `package` implicits? Unsure. Replace these with `import package._`

* Move the BaseModule object into the internal package.

1 files changed, 0 insertions, 122 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
deleted file mode 100644
index e30b91ec..00000000
--- a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
+++ /dev/null
@@ -1,122 +0,0 @@
-// See LICENSE for license details.
-
-package chisel3.core
-
-import chisel3.internal.ChiselException
-import chisel3.internal.Builder.{forcedModule}
-import chisel3.internal.firrtl.LitArg
-
-object Binding {
-  class BindingException(message: String) extends ChiselException(message)
-  /** A function expected a Chisel type but got a hardware object
-    */
-  case class ExpectedChiselTypeException(message: String) extends BindingException(message)
-  /**A function expected a hardware object but got a Chisel type
-    */
-  case class ExpectedHardwareException(message: String) extends BindingException(message)
-  /** An aggregate had a mix of specified and unspecified directionality children
-    */
-  case class MixedDirectionAggregateException(message: String) extends BindingException(message)
-  /** Attempted to re-bind an already bound (directionality or hardware) object
-    */
-  case class RebindingException(message: String) extends BindingException(message)
-}
-
-/** Requires that a node is hardware ("bound")
-  */
-object requireIsHardware {
-  def apply(node: Data, msg: String = ""): Unit = {
-    node._parent match {  // Compatibility layer hack
-      case Some(x: BaseModule) => x._compatAutoWrapPorts
-      case _ =>
-    }
-    if (!node.isSynthesizable) {
-      val prefix = if (msg.nonEmpty) s"$msg " else ""
-      throw Binding.ExpectedHardwareException(s"$prefix'$node' must be hardware, " +
-        "not a bare Chisel type. Perhaps you forgot to wrap it in Wire(_) or IO(_)?")
-    }
-  }
-}
-
-/** Requires that a node is a chisel type (not hardware, "unbound")
-  */
-object requireIsChiselType {
-  def apply(node: Data, msg: String = ""): Unit = if (node.isSynthesizable) {
-    val prefix = if (msg.nonEmpty) s"$msg " else ""
-    throw Binding.ExpectedChiselTypeException(s"$prefix'$node' must be a Chisel type, not hardware")
-  }
-}
-
-// Element only direction used for the Binding system only.
-sealed abstract class BindingDirection
-object BindingDirection {
-  /** Internal type or wire
-    */
-  case object Internal extends BindingDirection
-  /** Module port with output direction
-    */
-  case object Output extends BindingDirection
-  /** Module port with input direction
-    */
-  case object Input extends BindingDirection
-
-  /** Determine the BindingDirection of an Element given its top binding and resolved direction.
-    */
-  def from(binding: TopBinding, direction: ActualDirection): BindingDirection = {
-    binding match {
-      case PortBinding(_) => direction match {
-        case ActualDirection.Output => Output
-        case ActualDirection.Input => Input
-        case dir => throw new RuntimeException(s"Unexpected port element direction '$dir'")
-      }
-      case _ => Internal
-    }
-  }
-}
-
-// Location refers to 'where' in the Module hierarchy this lives
-sealed trait Binding {
-  def location: Option[BaseModule]
-}
-// Top-level binding representing hardware, not a pointer to another binding (like ChildBinding)
-sealed trait TopBinding extends Binding
-
-// Constrained-ness refers to whether 'bound by Module boundaries'
-// An unconstrained binding, like a literal, can be read by everyone
-sealed trait UnconstrainedBinding extends TopBinding {
-  def location: Option[BaseModule] = None
-}
-// A constrained binding can only be read/written by specific modules
-// Location will track where this Module is, and the bound object can be referenced in FIRRTL
-sealed trait ConstrainedBinding extends TopBinding {
-  def enclosure: BaseModule
-  def location: Option[BaseModule] = Some(enclosure)
-}
-
-// A binding representing a data that cannot be (re)assigned to.
-sealed trait ReadOnlyBinding extends TopBinding
-
-// TODO(twigg): Ops between unenclosed nodes can also be unenclosed
-// However, Chisel currently binds all op results to a module
-case class OpBinding(enclosure: RawModule) extends ConstrainedBinding with ReadOnlyBinding
-case class MemoryPortBinding(enclosure: RawModule) extends ConstrainedBinding
-case class PortBinding(enclosure: BaseModule) extends ConstrainedBinding
-case class RegBinding(enclosure: RawModule) extends ConstrainedBinding
-case class WireBinding(enclosure: RawModule) extends ConstrainedBinding
-
-case class ChildBinding(parent: Data) extends Binding {
-  def location: Option[BaseModule] = parent.topBinding.location
-}
-/** Special binding for Vec.sample_element */
-case class SampleElementBinding[T <: Data](parent: Vec[T]) extends Binding {
-  def location = parent.topBinding.location
-}
-// A DontCare element has a specific Binding, somewhat like a literal.
-// It is a source (RHS). It may only be connected/applied to sinks.
-case class DontCareBinding() extends UnconstrainedBinding
-
-sealed trait LitBinding extends UnconstrainedBinding with ReadOnlyBinding
-// Literal binding attached to a element that is not part of a Bundle.
-case class ElementLitBinding(litArg: LitArg) extends LitBinding
-// Literal binding attached to the root of a Bundle, containing literal values of its children.
-case class BundleLitBinding(litMap: Map[Data, LitArg]) extends LitBinding