diff options
| author | Donggyu Kim | 2016-08-15 18:03:12 -0700 |
|---|---|---|
| committer | Donggyu Kim | 2016-08-21 22:28:03 -0700 |
| commit | 2d01fdf6f26f480cb7ed19c1365f181ea717ddc2 (patch) | |
| tree | 75eecb6157ada9471d17bc9fb082d091b969da34 /chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | |
| parent | 0744b3e5f9c0648878b97d3375cd7d88e2d0ee08 (diff) | |
provides signal name methods for firrtl annotation and chisel testers
* signalName: returns the chirrtl name of the signal
* pathName: returns the full path name of the signal from the top module
* parentPathName: returns the full path of the signal's parent module instance from the top module
* parentModName: returns the signal's parent **module(not instance)** name.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index de64cb3d..82c6097f 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -374,4 +374,5 @@ class Bundle extends Aggregate(NO_DIR) { private[core] object Bundle { val keywords = List("flip", "asInput", "asOutput", "cloneType", "toBits", - "widthOption", "signalName", "signalPathName", "signalParent", "signalComponent") + "widthOption", "signalName", "signalPathName", "signalParent", "signalComponent") +} |