From 2d01fdf6f26f480cb7ed19c1365f181ea717ddc2 Mon Sep 17 00:00:00 2001
From: Donggyu Kim
Date: Mon, 15 Aug 2016 18:03:12 -0700
Subject: provides signal name methods for firrtl annotation and chisel testers

* signalName: returns the chirrtl name of the signal

* pathName: returns the full path name of the signal from the top module

* parentPathName: returns the full path of the signal's parent module instance from the top module

* parentModName: returns the signal's parent **module(not instance)** name.
---
 chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index de64cb3d..82c6097f 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -374,4 +374,5 @@ class Bundle extends Aggregate(NO_DIR) {
 
 private[core] object Bundle {
   val keywords = List("flip", "asInput", "asOutput", "cloneType", "toBits",
-   "widthOption", "signalName", "signalPathName", "signalParent", "signalComponent")
+    "widthOption", "signalName", "signalPathName", "signalParent", "signalComponent")
+}
-- 
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