summaryrefslogtreecommitdiff
path: root/chiselFrontend/src/main/scala/chisel3/BoolFactory.scala
diff options
context:
space:
mode:
authorJack Koenig2020-03-25 19:51:46 -0700
committerGitHub2020-03-25 19:51:46 -0700
commitdbb024a9adee6d82f37e357cf8b55456674ff65c (patch)
tree578858ab6d219ca6daf44cf87b73f75054989097 /chiselFrontend/src/main/scala/chisel3/BoolFactory.scala
parent6263fcc56b630b7181eb30680cadcdbb2bdf91dc (diff)
parentfbf5e6f1a0e8bf535d465b748ad554575fe62156 (diff)
Merge pull request #1384 from freechipsproject/no-more-compile-internal
No more compile internal
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/BoolFactory.scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/BoolFactory.scala22
1 files changed, 0 insertions, 22 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/BoolFactory.scala b/chiselFrontend/src/main/scala/chisel3/BoolFactory.scala
deleted file mode 100644
index bccd6414..00000000
--- a/chiselFrontend/src/main/scala/chisel3/BoolFactory.scala
+++ /dev/null
@@ -1,22 +0,0 @@
-// See LICENSE for license details.
-
-package chisel3
-
-import chisel3.internal.firrtl.{ULit, Width}
-
-// scalastyle:off method.name
-
-trait BoolFactory {
- /** Creates an empty Bool.
- */
- def apply(): Bool = new Bool()
-
- /** Creates Bool literal.
- */
- protected[chisel3] def Lit(x: Boolean): Bool = {
- val result = new Bool()
- val lit = ULit(if (x) 1 else 0, Width(1))
- // Ensure we have something capable of generating a name.
- lit.bindLitArg(result)
- }
-}