diff options
| author | Leway Colin | 2020-01-25 09:42:59 +0800 |
|---|---|---|
| committer | mergify[bot] | 2020-01-25 01:42:59 +0000 |
| commit | f1c4395bd608234fef5a60d8851036d1acb2382f (patch) | |
| tree | 909fcefbc51c2c67a0984e2ef4f861be98e9d0ba /chiselFrontend/src/main/scala/chisel3/Aggregate.scala | |
| parent | 160e019e38c933112836cccbb38c5f397427cf7f (diff) | |
Fixed code example typo in comment (#1294)
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/Aggregate.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/Aggregate.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala index 8141fdba..84e959a5 100644 --- a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala @@ -121,7 +121,7 @@ trait VecFactory extends SourceInfoDoc { * {{{ * val io = IO(new Bundle { * val in = Input(Vec(20, UInt(16.W))) - * val addr = UInt(5.W) + * val addr = Input(UInt(5.W)) * val out = Output(UInt(16.W)) * }) * io.out := io.in(io.addr) @@ -696,8 +696,8 @@ package experimental { * val outPacket = Output(new Packet) * }) * val reg = Reg(new Packet) - * reg <> inPacket - * outPacket <> reg + * reg <> io.inPacket + * io.outPacket <> reg * } * }}} */ |