Merge branch 'master' into add-asbool-to-clock

1 files changed, 3 insertions, 3 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
index 8141fdba..84e959a5 100644
--- a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
@@ -121,7 +121,7 @@ trait VecFactory extends SourceInfoDoc {
   *  {{{
   *    val io = IO(new Bundle {
   *      val in = Input(Vec(20, UInt(16.W)))
-  *      val addr = UInt(5.W)
+  *      val addr = Input(UInt(5.W))
   *      val out = Output(UInt(16.W))
   *    })
   *    io.out := io.in(io.addr)
@@ -696,8 +696,8 @@ package experimental {
   *        val outPacket = Output(new Packet)
   *      })
   *      val reg = Reg(new Packet)
-  *      reg <> inPacket
-  *      outPacket <> reg
+  *      reg <> io.inPacket
+  *      io.outPacket <> reg
   *   }
   * }}}
   */