Package split chisel core

1 files changed, 6 insertions, 6 deletions

diff --git a/chiselFrontend/src/main/scala/chisel/core/Printf.scala b/chiselFrontend/src/main/scala/chisel/core/Printf.scala
index 27b72815..a7970816 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Printf.scala
+++ b/chiselFrontend/src/main/scala/chisel/core/Printf.scala
@@ -1,13 +1,13 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel.core
 
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.SourceInfo
+import chisel.internal._
+import chisel.internal.Builder.pushCommand
+import chisel.internal.firrtl._
+import chisel.internal.sourceinfo.SourceInfo
 
 object printf { // scalastyle:ignore object.name
   /** Prints a message in simulation.
@@ -29,7 +29,7 @@ object printf { // scalastyle:ignore object.name
     }
   }
 
-  private[chisel] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
+  private[core] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
     val clock = Builder.dynamicContext.currentModule.get.clock
     pushCommand(Printf(sourceInfo, Node(clock), fmt, data.map((d: Bits) => d.ref)))
   }