Package split chisel core

14 files changed, 89 insertions, 87 deletions

diff --git a/chiselFrontend/src/main/scala/chisel/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel/core/Aggregate.scala
index 4f3f3de0..38a42fea 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel/core/Aggregate.scala
@@ -1,21 +1,21 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel.core
 
 import scala.collection.immutable.ListMap
 import scala.collection.mutable.{ArrayBuffer, HashSet, LinkedHashMap}
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, VecTransform, SourceInfoTransform}
+import chisel.internal._
+import chisel.internal.Builder.pushCommand
+import chisel.internal.firrtl._
+import chisel.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, VecTransform, SourceInfoTransform}
 
 /** An abstract class for data types that solely consist of (are an aggregate
   * of) other Data objects.
   */
 sealed abstract class Aggregate(dirArg: Direction) extends Data(dirArg) {
-  private[chisel] def cloneTypeWidth(width: Width): this.type = cloneType
+  private[core] def cloneTypeWidth(width: Width): this.type = cloneType
   def width: Width = flatten.map(_.width).reduce(_ + _)
 }
 
@@ -315,7 +315,7 @@ class Bundle extends Aggregate(NO_DIR) {
 
   /** Returns a list of elements in this Bundle.
     */
-  private[chisel] lazy val namedElts = {
+  private[core] lazy val namedElts = {
     val nameMap = LinkedHashMap[String, Data]()
     val seen = HashSet[Data]()
     for (m <- getClass.getMethods.sortWith(_.getName < _.getName)) {
@@ -339,7 +339,7 @@ class Bundle extends Aggregate(NO_DIR) {
     s"{${namedElts.reverse.map(e => eltPort(e._2)).mkString(", ")}}"
   }
   private[chisel] lazy val flatten = namedElts.flatMap(_._2.flatten)
-  private[chisel] def addElt(name: String, elt: Data): Unit =
+  private[core] def addElt(name: String, elt: Data): Unit =
     namedElts += name -> elt
   private[chisel] override def _onModuleClose: Unit = // scalastyle:ignore method.name
     for ((name, elt) <- namedElts) { elt.setRef(this, _namespace.name(name)) }
@@ -372,6 +372,6 @@ class Bundle extends Aggregate(NO_DIR) {
   }
 }
 
-private[chisel] object Bundle {
+private[core] object Bundle {
   val keywords = List("flip", "asInput", "asOutput", "cloneType", "toBits")
 }
diff --git a/chiselFrontend/src/main/scala/chisel/core/Assert.scala b/chiselFrontend/src/main/scala/chisel/core/Assert.scala
index 0d660bc3..00cb00f4 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Assert.scala
+++ b/chiselFrontend/src/main/scala/chisel/core/Assert.scala
@@ -1,14 +1,14 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel.core
 
 import scala.reflect.macros.blackbox.Context
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.SourceInfo
+import chisel.internal._
+import chisel.internal.Builder.pushCommand
+import chisel.internal.firrtl._
+import chisel.internal.sourceinfo.SourceInfo
 
 object assert { // scalastyle:ignore object.name
   /** Checks for a condition to be valid in the circuit at all times. If the
diff --git a/chiselFrontend/src/main/scala/chisel/core/Bits.scala b/chiselFrontend/src/main/scala/chisel/core/Bits.scala
index 8ec7c1b9..38e71f8d 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel/core/Bits.scala
@@ -1,15 +1,15 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel.core
 
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushOp
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, SourceInfoTransform, SourceInfoWhiteboxTransform,
+import chisel.internal._
+import chisel.internal.Builder.pushOp
+import chisel.internal.firrtl._
+import chisel.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, SourceInfoTransform, SourceInfoWhiteboxTransform,
   UIntTransform, MuxTransform}
-import firrtl.PrimOp._
+import chisel.internal.firrtl.PrimOp._
 
 /** Element is a leaf data type: it cannot contain other Data objects. Example
   * uses are for representing primitive data types, like integers and bits.
@@ -118,16 +118,16 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
   final def do_apply(x: BigInt, y: BigInt)(implicit sourceInfo: SourceInfo): UInt =
     apply(x.toInt, y.toInt)
 
-  private[chisel] def unop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp): T =
+  private[core] def unop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp): T =
     pushOp(DefPrim(sourceInfo, dest, op, this.ref))
-  private[chisel] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: BigInt): T =
+  private[core] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: BigInt): T =
     pushOp(DefPrim(sourceInfo, dest, op, this.ref, ILit(other)))
-  private[chisel] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: Bits): T =
+  private[core] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: Bits): T =
     pushOp(DefPrim(sourceInfo, dest, op, this.ref, other.ref))
 
-  private[chisel] def compop(sourceInfo: SourceInfo, op: PrimOp, other: Bits): Bool =
+  private[core] def compop(sourceInfo: SourceInfo, op: PrimOp, other: Bits): Bool =
     pushOp(DefPrim(sourceInfo, Bool(), op, this.ref, other.ref))
-  private[chisel] def redop(sourceInfo: SourceInfo, op: PrimOp): Bool =
+  private[core] def redop(sourceInfo: SourceInfo, op: PrimOp): Bool =
     pushOp(DefPrim(sourceInfo, Bool(), op, this.ref))
 
   /** Returns this wire zero padded up to the specified width.
@@ -356,9 +356,9 @@ abstract trait Num[T <: Data] {
 /** A data type for unsigned integers, represented as a binary bitvector.
   * Defines arithmetic operations between other integer types.
   */
-sealed class UInt private[chisel] (dir: Direction, width: Width, lit: Option[ULit] = None)
+sealed class UInt private[core] (dir: Direction, width: Width, lit: Option[ULit] = None)
     extends Bits(dir, width, lit) with Num[UInt] {
-  private[chisel] override def cloneTypeWidth(w: Width): this.type =
+  private[core] override def cloneTypeWidth(w: Width): this.type =
     new UInt(dir, w).asInstanceOf[this.type]
   private[chisel] def toType = s"UInt$width"
 
@@ -482,7 +482,7 @@ sealed class UInt private[chisel] (dir: Direction, width: Width, lit: Option[ULi
 }
 
 // This is currently a factory because both Bits and UInt inherit it.
-private[chisel] sealed trait UIntFactory {
+private[core] sealed trait UIntFactory {
   /** Create a UInt type with inferred width. */
   def apply(): UInt = apply(NO_DIR, Width())
   /** Create a UInt type or port with fixed width. */
@@ -535,7 +535,7 @@ object UInt extends UIntFactory
 
 sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = None)
     extends Bits(dir, width, lit) with Num[SInt] {
-  private[chisel] override def cloneTypeWidth(w: Width): this.type =
+  private[core] override def cloneTypeWidth(w: Width): this.type =
     new SInt(dir, w).asInstanceOf[this.type]
   private[chisel] def toType = s"SInt$width"
 
@@ -666,7 +666,7 @@ object SInt {
 /** A data type for booleans, defined as a single bit indicating true or false.
   */
 sealed class Bool(dir: Direction, lit: Option[ULit] = None) extends UInt(dir, Width(1), lit) {
-  private[chisel] override def cloneTypeWidth(w: Width): this.type = {
+  private[core] override def cloneTypeWidth(w: Width): this.type = {
     require(!w.known || w.get == 1)
     new Bool(dir).asInstanceOf[this.type]
   }
diff --git a/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala
index 1dabc18f..2126ebce 100644
--- a/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel.core
 
-import internal.Builder.pushCommand
-import internal.firrtl.{ModuleIO, DefInvalid}
-import internal.sourceinfo.SourceInfo
+import chisel.internal.Builder.pushCommand
+import chisel.internal.firrtl.{ModuleIO, DefInvalid}
+import chisel.internal.sourceinfo.SourceInfo
 
 /** Defines a black box, which is a module that can be referenced from within
   * Chisel, but is not defined in the emitted Verilog. Useful for connecting
@@ -24,10 +24,10 @@ abstract class BlackBox extends Module {
   // The body of a BlackBox is empty, the real logic happens in firrtl/Emitter.scala
   // Bypass standard clock, reset, io port declaration by flattening io
   // TODO(twigg): ? Really, overrides are bad, should extend BaseModule....
-  override private[chisel] def ports = io.elements.toSeq
+  override private[core] def ports = io.elements.toSeq
 
   // Do not do reflective naming of internal signals, just name io
-  override private[chisel] def setRefs(): this.type = {
+  override private[core] def setRefs(): this.type = {
     for ((name, port) <- ports) {
       port.setRef(ModuleIO(this, _namespace.name(name)))
     }
@@ -40,7 +40,7 @@ abstract class BlackBox extends Module {
 
   // Don't setup clock, reset
   // Cann't invalide io in one bunch, must invalidate each part separately
-  override private[chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = _parent match {
+  override private[core] def setupInParent(implicit sourceInfo: SourceInfo): this.type = _parent match {
     case Some(p) => {
       // Just init instance inputs
       for((_,port) <- ports) pushCommand(DefInvalid(sourceInfo, port.ref))
diff --git a/chiselFrontend/src/main/scala/chisel/core/Data.scala b/chiselFrontend/src/main/scala/chisel/core/Data.scala
index c08adf9d..077c4893 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel/core/Data.scala
@@ -1,13 +1,13 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel.core
 
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
+import chisel.internal._
+import chisel.internal.Builder.pushCommand
+import chisel.internal.firrtl._
+import chisel.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
 
 sealed abstract class Direction(name: String) {
   override def toString: String = name
@@ -38,9 +38,9 @@ abstract class Data(dirArg: Direction) extends HasId {
   // Sucks this is mutable state, but cloneType doesn't take a Direction arg
   private var isFlipVar = dirArg == INPUT
   private var dirVar = dirArg
-  private[chisel] def isFlip = isFlipVar
+  private[core] def isFlip = isFlipVar
 
-  private[chisel] def overrideDirection(newDir: Direction => Direction,
+  private[core] def overrideDirection(newDir: Direction => Direction,
                                         newFlip: Boolean => Boolean): this.type = {
     this.isFlipVar = newFlip(this.isFlipVar)
     for (field <- this.flatten)
@@ -51,15 +51,15 @@ abstract class Data(dirArg: Direction) extends HasId {
   def asOutput: this.type = cloneType.overrideDirection(_ => OUTPUT, _ => false)
   def flip(): this.type = cloneType.overrideDirection(_.flip, !_)
 
-  private[chisel] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+  private[core] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     throwException(s"cannot connect ${this} and ${that}")
-  private[chisel] def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+  private[core] def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     pushCommand(Connect(sourceInfo, this.lref, that.ref))
-  private[chisel] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+  private[core] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))
-  private[chisel] def lref: Node = Node(this)
+  private[core] def lref: Node = Node(this)
   private[chisel] def ref: Arg = if (isLit) litArg.get else lref
-  private[chisel] def cloneTypeWidth(width: Width): this.type
+  private[core] def cloneTypeWidth(width: Width): this.type
   private[chisel] def toType: String
 
   def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this badConnect that
@@ -151,7 +151,7 @@ object Clock {
 sealed class Clock(dirArg: Direction) extends Element(dirArg, Width(1)) {
   def cloneType: this.type = Clock(dirArg).asInstanceOf[this.type]
   private[chisel] override def flatten: IndexedSeq[Bits] = IndexedSeq()
-  private[chisel] def cloneTypeWidth(width: Width): this.type = cloneType
+  private[core] def cloneTypeWidth(width: Width): this.type = cloneType
   private[chisel] def toType = "Clock"
 
   override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
diff --git a/chiselFrontend/src/main/scala/chisel/core/Mem.scala b/chiselFrontend/src/main/scala/chisel/core/Mem.scala
index 5fd8b81e..a2df2910 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel/core/Mem.scala
@@ -1,13 +1,13 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel.core
 
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, MemTransform}
+import chisel.internal._
+import chisel.internal.Builder.pushCommand
+import chisel.internal.firrtl._
+import chisel.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, MemTransform}
 
 object Mem {
   @deprecated("Mem argument order should be size, t; this will be removed by the official release", "chisel3")
diff --git a/chiselFrontend/src/main/scala/chisel/core/Module.scala b/chiselFrontend/src/main/scala/chisel/core/Module.scala
index f7f8c0b5..1de3efe5 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel/core/Module.scala
@@ -1,15 +1,15 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel.core
 
 import scala.collection.mutable.{ArrayBuffer, HashSet}
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.Builder.dynamicContext
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, InstTransform, UnlocatableSourceInfo}
+import chisel.internal._
+import chisel.internal.Builder.pushCommand
+import chisel.internal.Builder.dynamicContext
+import chisel.internal.firrtl._
+import chisel.internal.sourceinfo.{SourceInfo, InstTransform, UnlocatableSourceInfo}
 
 object Module {
   /** A wrapper method that all Module instantiations must be wrapped in
@@ -52,9 +52,9 @@ extends HasId {
   def this(_reset: Bool)  = this(None, Option(_reset))
   def this(_clock: Clock, _reset: Bool) = this(Option(_clock), Option(_reset))
 
-  private[chisel] val _namespace = Builder.globalNamespace.child
+  private[core] val _namespace = Builder.globalNamespace.child
   private[chisel] val _commands = ArrayBuffer[Command]()
-  private[chisel] val _ids = ArrayBuffer[HasId]()
+  private[core] val _ids = ArrayBuffer[HasId]()
   dynamicContext.currentModule = Some(this)
 
   /** Name of the instance. */
@@ -69,16 +69,16 @@ extends HasId {
 
   private[chisel] def addId(d: HasId) { _ids += d }
 
-  private[chisel] def ports: Seq[(String,Data)] = Vector(
+  private[core] def ports: Seq[(String,Data)] = Vector(
     ("clk", clock), ("reset", reset), ("io", io)
   )
 
-  private[chisel] def computePorts = for((name, port) <- ports) yield {
+  private[core] def computePorts = for((name, port) <- ports) yield {
     val bundleDir = if (port.isFlip) INPUT else OUTPUT
     Port(port, if (port.dir == NO_DIR) bundleDir else port.dir)
   }
 
-  private[chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = {
+  private[core] def setupInParent(implicit sourceInfo: SourceInfo): this.type = {
     _parent match {
       case Some(p) => {
         pushCommand(DefInvalid(sourceInfo, io.ref)) // init instance inputs
@@ -90,7 +90,7 @@ extends HasId {
     }
   }
 
-  private[chisel] def setRefs(): this.type = {
+  private[core] def setRefs(): this.type = {
     for ((name, port) <- ports) {
       port.setRef(ModuleIO(this, _namespace.name(name)))
     }
diff --git a/chiselFrontend/src/main/scala/chisel/core/Printf.scala b/chiselFrontend/src/main/scala/chisel/core/Printf.scala
index 27b72815..a7970816 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Printf.scala
+++ b/chiselFrontend/src/main/scala/chisel/core/Printf.scala
@@ -1,13 +1,13 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel.core
 
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.SourceInfo
+import chisel.internal._
+import chisel.internal.Builder.pushCommand
+import chisel.internal.firrtl._
+import chisel.internal.sourceinfo.SourceInfo
 
 object printf { // scalastyle:ignore object.name
   /** Prints a message in simulation.
@@ -29,7 +29,7 @@ object printf { // scalastyle:ignore object.name
     }
   }
 
-  private[chisel] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
+  private[core] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
     val clock = Builder.dynamicContext.currentModule.get.clock
     pushCommand(Printf(sourceInfo, Node(clock), fmt, data.map((d: Bits) => d.ref)))
   }
diff --git a/chiselFrontend/src/main/scala/chisel/core/Reg.scala b/chiselFrontend/src/main/scala/chisel/core/Reg.scala
index 0ed320d7..78461334 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Reg.scala
+++ b/chiselFrontend/src/main/scala/chisel/core/Reg.scala
@@ -1,14 +1,14 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel.core
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo}
+import chisel.internal._
+import chisel.internal.Builder.pushCommand
+import chisel.internal.firrtl._
+import chisel.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo}
 
 object Reg {
-  private[chisel] def makeType[T <: Data](t: T = null, next: T = null, init: T = null): T = {
+  private[core] def makeType[T <: Data](t: T = null, next: T = null, init: T = null): T = {
     if (t ne null) {
       t.cloneType
     } else if (next ne null) {
diff --git a/chiselFrontend/src/main/scala/chisel/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel/core/SeqUtils.scala
index da75edae..e31119a5 100644
--- a/chiselFrontend/src/main/scala/chisel/core/SeqUtils.scala
+++ b/chiselFrontend/src/main/scala/chisel/core/SeqUtils.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel.core
 
 import scala.language.experimental.macros
 
-import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
+import chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
 
 private[chisel] object SeqUtils {
   /** Equivalent to Cat(r(n-1), ..., r(0)) */
diff --git a/chiselFrontend/src/main/scala/chisel/core/When.scala b/chiselFrontend/src/main/scala/chisel/core/When.scala
index 37c59f24..5d484313 100644
--- a/chiselFrontend/src/main/scala/chisel/core/When.scala
+++ b/chiselFrontend/src/main/scala/chisel/core/When.scala
@@ -1,13 +1,13 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel.core
 
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo}
+import chisel.internal._
+import chisel.internal.Builder.pushCommand
+import chisel.internal.firrtl._
+import chisel.internal.sourceinfo.{SourceInfo}
 
 object when {  // scalastyle:ignore object.name
   /** Create a `when` condition block, where whether a block of logic is
diff --git a/chiselFrontend/src/main/scala/chisel/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel/internal/Builder.scala
index bacde365..9c0a3514 100644
--- a/chiselFrontend/src/main/scala/chisel/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel/internal/Builder.scala
@@ -6,6 +6,7 @@ import scala.util.DynamicVariable
 import scala.collection.mutable.{ArrayBuffer, HashMap}
 
 import chisel._
+import core._
 import firrtl._
 
 private[chisel] class Namespace(parent: Option[Namespace], keywords: Set[String]) {
diff --git a/chiselFrontend/src/main/scala/chisel/internal/Error.scala b/chiselFrontend/src/main/scala/chisel/internal/Error.scala
index 256a6d7f..f0481dc4 100644
--- a/chiselFrontend/src/main/scala/chisel/internal/Error.scala
+++ b/chiselFrontend/src/main/scala/chisel/internal/Error.scala
@@ -4,7 +4,7 @@ package chisel.internal
 
 import scala.collection.mutable.ArrayBuffer
 
-import chisel._
+import chisel.core._
 
 class ChiselException(message: String, cause: Throwable) extends Exception(message, cause)
 
diff --git a/chiselFrontend/src/main/scala/chisel/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel/internal/firrtl/IR.scala
index 9c1ce98e..70e9938b 100644
--- a/chiselFrontend/src/main/scala/chisel/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel/internal/firrtl/IR.scala
@@ -3,6 +3,7 @@
 package chisel.internal.firrtl
 
 import chisel._
+import core._
 import chisel.internal._
 import chisel.internal.sourceinfo.{SourceInfo, NoSourceInfo}