Package split chisel core

1 files changed, 7 insertions, 7 deletions

diff --git a/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala
index 1dabc18f..2126ebce 100644
--- a/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel.core
 
-import internal.Builder.pushCommand
-import internal.firrtl.{ModuleIO, DefInvalid}
-import internal.sourceinfo.SourceInfo
+import chisel.internal.Builder.pushCommand
+import chisel.internal.firrtl.{ModuleIO, DefInvalid}
+import chisel.internal.sourceinfo.SourceInfo
 
 /** Defines a black box, which is a module that can be referenced from within
   * Chisel, but is not defined in the emitted Verilog. Useful for connecting
@@ -24,10 +24,10 @@ abstract class BlackBox extends Module {
   // The body of a BlackBox is empty, the real logic happens in firrtl/Emitter.scala
   // Bypass standard clock, reset, io port declaration by flattening io
   // TODO(twigg): ? Really, overrides are bad, should extend BaseModule....
-  override private[chisel] def ports = io.elements.toSeq
+  override private[core] def ports = io.elements.toSeq
 
   // Do not do reflective naming of internal signals, just name io
-  override private[chisel] def setRefs(): this.type = {
+  override private[core] def setRefs(): this.type = {
     for ((name, port) <- ports) {
       port.setRef(ModuleIO(this, _namespace.name(name)))
     }
@@ -40,7 +40,7 @@ abstract class BlackBox extends Module {
 
   // Don't setup clock, reset
   // Cann't invalide io in one bunch, must invalidate each part separately
-  override private[chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = _parent match {
+  override private[core] def setupInParent(implicit sourceInfo: SourceInfo): this.type = _parent match {
     case Some(p) => {
       // Just init instance inputs
       for((_,port) <- ports) pushCommand(DefInvalid(sourceInfo, port.ref))