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authorducky2016-06-01 12:46:05 -0700
committerducky2016-06-08 16:22:28 -0700
commit69c984607e87cb62c82c99056b2664f11b968267 (patch)
tree170bce1cf0f4f3e9ec27ea47660daf10bfc4aeea /chiselFrontend/src/main/scala/chisel/core/Assert.scala
parent66301b9042530a5265c18c97a0dab9022a0efc50 (diff)
Package split chisel core
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel/core/Assert.scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel/core/Assert.scala10
1 files changed, 5 insertions, 5 deletions
diff --git a/chiselFrontend/src/main/scala/chisel/core/Assert.scala b/chiselFrontend/src/main/scala/chisel/core/Assert.scala
index 0d660bc3..00cb00f4 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Assert.scala
+++ b/chiselFrontend/src/main/scala/chisel/core/Assert.scala
@@ -1,14 +1,14 @@
// See LICENSE for license details.
-package chisel
+package chisel.core
import scala.reflect.macros.blackbox.Context
import scala.language.experimental.macros
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.SourceInfo
+import chisel.internal._
+import chisel.internal.Builder.pushCommand
+import chisel.internal.firrtl._
+import chisel.internal.sourceinfo.SourceInfo
object assert { // scalastyle:ignore object.name
/** Checks for a condition to be valid in the circuit at all times. If the