summaryrefslogtreecommitdiff
path: root/chiselFrontend/src/main/scala/Chisel/Printf.scala
diff options
context:
space:
mode:
authorducky2016-05-20 18:09:57 -0700
committerducky2016-06-08 16:22:27 -0700
commitf36524e388b060b1bb535ae21cb1bcbbea220be9 (patch)
treea32772f816f18b14002948964917be0cb8280c48 /chiselFrontend/src/main/scala/Chisel/Printf.scala
parent53813f61b7dfe246d214ab966739d01c65c8ecb0 (diff)
Rename packages to lowercase chisel, add compatibility layer
Diffstat (limited to 'chiselFrontend/src/main/scala/Chisel/Printf.scala')
-rw-r--r--chiselFrontend/src/main/scala/Chisel/Printf.scala36
1 files changed, 0 insertions, 36 deletions
diff --git a/chiselFrontend/src/main/scala/Chisel/Printf.scala b/chiselFrontend/src/main/scala/Chisel/Printf.scala
deleted file mode 100644
index f068f637..00000000
--- a/chiselFrontend/src/main/scala/Chisel/Printf.scala
+++ /dev/null
@@ -1,36 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-
-import scala.language.experimental.macros
-
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.SourceInfo
-
-object printf { // scalastyle:ignore object.name
- /** Prints a message in simulation.
- *
- * Does not fire when in reset (defined as the encapsulating Module's
- * reset). If your definition of reset is not the encapsulating Module's
- * reset, you will need to gate this externally.
- *
- * May be called outside of a Module (like defined in a function), so
- * functions using printf make the standard Module assumptions (single clock
- * and single reset).
- *
- * @param fmt printf format string
- * @param data format string varargs containing data to print
- */
- def apply(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
- when (!(Builder.dynamicContext.currentModule.get.reset)) {
- printfWithoutReset(fmt, data:_*)
- }
- }
-
- private[Chisel] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
- val clock = Builder.dynamicContext.currentModule.get.clock
- pushCommand(Printf(sourceInfo, Node(clock), fmt, data.map((d: Bits) => d.ref)))
- }
-}