added elaboration tests for remaining old Chisel3 examples

13 files changed, 755 insertions, 36 deletions

diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
index d1ea0dd7..1aa2aaba 100644
--- a/src/test/scala/chiselTests/Counter.scala
+++ b/src/test/scala/chiselTests/Counter.scala
@@ -17,7 +17,7 @@ class EnableTester(seed: Int) extends BasicTester {
   ens := ens >> 1
   val (cntEn, cntWrap) = Counter(ens(0), 32)
   val cnt = Counter(Bool(true), 32)._1
-  when(cnt === UInt(30)) {
+  when(cnt === UInt(31)) {
     io.done := Bool(true)
     io.error := cnt != UInt(popCount(seed))
   }
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
new file mode 100644
index 00000000..b19fe3d9
--- /dev/null
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -0,0 +1,53 @@
+// See LICENSE for license details.
+
+package chiselTests
+import Chisel._
+import Chisel.testers.BasicTester
+
+class EnableShiftRegister extends Module {
+  val io = new Bundle {
+    val in    = UInt(INPUT, 4)
+    val shift = Bool(INPUT)
+    val out   = UInt(OUTPUT, 4)
+  }
+  val r0 = Reg(init = UInt(0, 4))
+  val r1 = Reg(init = UInt(0, 4))
+  val r2 = Reg(init = UInt(0, 4))
+  val r3 = Reg(init = UInt(0, 4))
+  when(io.shift) {
+    r0 := io.in
+    r1 := r0
+    r2 := r1
+    r3 := r2
+  }
+  io.out := r3
+}
+
+/*
+class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) {
+  val reg = Array.fill(4){ 0 }
+  for (t <- 0 until 16) {
+    val in    = rnd.nextInt(16)
+    val shift = rnd.nextInt(2)
+    println("SHIFT " + shift + " IN " + in)
+    poke(c.io.in,    in)
+    poke(c.io.shift, shift)
+    step(1)
+    if (shift == 1) {
+      for (i <- 3 to 1 by -1)
+        reg(i) = reg(i-1)
+      reg(0) = in
+    }
+    expect(c.io.out, reg(3))
+  }
+}
+*/
+
+class EnableShiftRegisterSpec extends ChiselPropSpec {
+  
+  property("EnableShiftRegister should elaborate") {
+    elaborate { new EnableShiftRegister }
+  }
+
+  ignore("EnableShiftRegisterTester should return the correct result") { }
+}
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index acc1e84e..27e147f4 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -48,7 +48,11 @@ class GCDSpec extends ChiselPropSpec {
     ( 12,   9,   3),
     ( 48,  64,  12))
 
-  property("GCD should return the correct result") {
+  property("GCD should elaborate") {
+    elaborate { new GCD }
+  }
+
+  property("GCDTester should return the correct result") {
     forAll (gcds) { (a: Int, b: Int, z: Int) =>
       assert(execute{ new GCDTester(a, b, z) })
     }
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
new file mode 100644
index 00000000..dcc3a403
--- /dev/null
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -0,0 +1,46 @@
+// See LICENSE for license details.
+
+package chiselTests
+import Chisel._
+import Chisel.testers.BasicTester
+
+class LFSR16 extends Module {
+  val io = new Bundle {
+    val inc = Bool(INPUT)
+    val out = UInt(OUTPUT, 16)
+  }
+  val res = Reg(init = UInt(1, 16))
+  when (io.inc) { 
+    val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1)) 
+    res := nxt_res
+  }
+  io.out := res
+}
+
+
+/*
+class LFSR16Tester(c: LFSR16) extends Tester(c) {
+  var res = 1
+  for (t <- 0 until 16) {
+    val inc = rnd.nextInt(2)
+    poke(c.io.inc, inc)
+    step(1)
+    if (inc == 1) {
+      val bit = ((res >> 0) ^ (res >> 2) ^ (res >> 3) ^ (res >> 5) ) & 1;
+      res = (res >> 1) | (bit << 15);
+    }
+    expect(c.io.out, res)
+  }
+}
+*/
+
+//TODO: Use chisel.util version instead?
+
+class LFSRSpec extends ChiselPropSpec {
+  
+  property("LFSR16 should elaborate") {
+    elaborate { new LFSR16 }
+  }
+
+  ignore("LFSR16 should return the correct result") { }
+}
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
new file mode 100644
index 00000000..ec48c666
--- /dev/null
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -0,0 +1,57 @@
+// See LICENSE for license details.
+
+package chiselTests
+import Chisel._
+import Chisel.testers.BasicTester
+
+class MemorySearch extends Module {
+  val io = new Bundle {
+    val target  = UInt(INPUT,  4)
+    val en      = Bool(INPUT)
+    val done    = Bool(OUTPUT)
+    val address = UInt(OUTPUT, 3)
+  }
+  val vals  = Array(0, 4, 15, 14, 2, 5, 13)
+  val index = Reg(init = UInt(0, width = 3))
+  val elts  = Vec(vals.map(UInt(_,4)))
+  // val elts  = Mem(UInt(width = 32), 8) TODO ????
+  val elt  = elts(index)
+  val end  = !io.en && ((elt === io.target) || (index === UInt(7)))
+  when (io.en) {
+    index := UInt(0)
+  } .elsewhen (!end) {
+    index := index +% UInt(1)
+  }
+  io.done    := end
+  io.address := index
+}
+
+/*
+class MemorySearchTester(c: MemorySearch) extends Tester(c) {
+  val list = c.vals
+  val n = 8
+  val maxT = n * (list.length + 3)
+  for (k <- 0 until n) {
+    val target = rnd.nextInt(16)
+    poke(c.io.en,     1)
+    poke(c.io.target, target)
+    step(1)
+    poke(c.io.en,     0)
+    do {
+      step(1)
+    } while (peek(c.io.done) == 0 && t < maxT)
+    val addr = peek(c.io.address).toInt
+    expect(addr == list.length || list(addr) == target, 
+           "LOOKING FOR " + target + " FOUND " + addr)
+  }
+}
+*/
+
+class MemorySearchSpec extends ChiselPropSpec {
+  
+  property("MemorySearch should elaborate") {
+    elaborate { new EnableShiftRegister }
+  }
+
+  ignore("MemorySearch should return the correct result") { }
+}
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
new file mode 100644
index 00000000..4191eea7
--- /dev/null
+++ b/src/test/scala/chiselTests/Module.scala
@@ -0,0 +1,90 @@
+// See LICENSE for license details.
+
+package chiselTests
+import Chisel._
+
+class SimpleIO extends Bundle {
+  val in  = UInt(INPUT,  32)
+  val out = UInt(OUTPUT, 32)
+}
+
+class PlusOne extends Module {
+  val io = new SimpleIO
+  io.out := io.in + UInt(1)
+}
+
+class ModuleVec(val n: Int) extends Module {
+  val io = new Bundle {
+    val ins  = Vec(UInt(INPUT,  32), n)
+    val outs = Vec(UInt(OUTPUT, 32), n)
+  }
+  val pluses = Vec.fill(n){ Module(new PlusOne).io }
+  for (i <- 0 until n) {
+    pluses(i).in := io.ins(i)
+    io.outs(i)   := pluses(i).out 
+  }
+}
+
+/*
+class ModuleVecTester(c: ModuleVec) extends Tester(c) {
+  for (t <- 0 until 16) {
+    val test_ins = Array.fill(c.n){ rnd.nextInt(256) }
+    for (i <- 0 until c.n) 
+      poke(c.io.ins(i), test_ins(i))
+    step(1)
+    for (i <- 0 until c.n) 
+      expect(c.io.outs(i), test_ins(i) + 1)
+  }
+}
+*/
+
+class ModuleWire extends Module {
+  val io = new SimpleIO
+  val inc = Wire(Module(new PlusOne).io)
+  inc.in := io.in
+  io.out := inc.out 
+}
+
+/*
+class ModuleWireTester(c: ModuleWire) extends Tester(c) {
+  for (t <- 0 until 16) {
+    val test_in = rnd.nextInt(256)
+    poke(c.io.in, test_in)
+    step(1)
+    expect(c.io.out, test_in + 1)
+  }
+}
+*/
+
+class ModuleWhen extends Module {
+  val io = new Bundle {
+    val s = new SimpleIO
+    val en = Bool()
+  }
+  when(io.en) { 
+    val inc = Module(new PlusOne).io
+    inc.in := io.s.in
+    io.s.out := inc.out 
+  } otherwise { io.s.out := io.s.in }
+}
+
+class ModuleSpec extends ChiselPropSpec {
+  
+  property("ModuleVec should elaborate") {
+    elaborate { new ModuleVec(2) }
+  }
+
+  ignore("ModuleVecTester should return the correct result") { }
+  
+  property("ModuleWire should elaborate") {
+    elaborate { new ModuleWire }
+  }
+
+  ignore("ModuleWireTester should return the correct result") { }
+  
+  property("ModuleWhen should elaborate") {
+    elaborate { new ModuleWhen }
+  }
+
+  ignore("ModuleWhenTester should return the correct result") { }
+}
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
new file mode 100644
index 00000000..35a4c4a6
--- /dev/null
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -0,0 +1,41 @@
+// See LICENSE for license details.
+
+package chiselTests
+import Chisel._
+
+class Padder extends Module {
+  val io = new Bundle {
+    val a   = Bits(INPUT,  4)
+    val asp = SInt(OUTPUT, 8)
+    val aup = UInt(OUTPUT, 8)
+  }
+  io.asp := io.a.toSInt
+  io.aup := io.a.toUInt
+}
+
+/*
+class PadsTester(c: Pads) extends Tester(c) {
+  def pads(x: BigInt, s: Int, w: Int) = {
+    val sign  = (x & (1 << (s-1)))
+    val wmask = (1 << w) - 1
+    val bmask = (1 << s) - 1
+    if (sign == 0) x else ((~bmask | x) & wmask)
+  }
+  for (t <- 0 until 16) {
+    val test_a = rnd.nextInt(1 << 4)
+    poke(c.io.a, test_a)
+    step(1)
+    expect(c.io.asp, pads(test_a, 4, 8))
+    expect(c.io.aup, test_a)
+  }
+}
+*/
+
+class PadderSpec extends ChiselPropSpec {
+  
+  property("Padder should elaborate") {
+    elaborate { new Padder }
+  }
+
+  ignore("PadderTester should return the correct result") { }
+}
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
new file mode 100644
index 00000000..b33b896b
--- /dev/null
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -0,0 +1,119 @@
+// See LICENSE for license details.
+
+package chiselTests
+import Chisel._
+
+class Risc extends Module {
+  val io = new Bundle {
+    val isWr   = Bool(INPUT)
+    val wrAddr = UInt(INPUT, 8)
+    val wrData = Bits(INPUT, 32)
+    val boot   = Bool(INPUT)
+    val valid  = Bool(OUTPUT)
+    val out    = Bits(OUTPUT, 32)
+  }
+  val file = Mem(Bits(width = 32), 256)
+  val code = Mem(Bits(width = 32), 256)
+  val pc   = Reg(init=UInt(0, 8))
+  
+  val add_op :: imm_op :: Nil = Enum(Bits(width = 8), 2)
+
+  val inst = code(pc)
+  val op   = inst(31,24)
+  val rci  = inst(23,16)
+  val rai  = inst(15, 8)
+  val rbi  = inst( 7, 0)
+
+  val ra = Mux(rai === Bits(0), Bits(0), file(rai))
+  val rb = Mux(rbi === Bits(0), Bits(0), file(rbi))
+  val rc = Wire(Bits(width = 32))
+
+  io.valid := Bool(false)
+  io.out   := Bits(0)
+  rc       := Bits(0)
+
+  when (io.isWr) {
+    code(io.wrAddr) := io.wrData
+  } .elsewhen (io.boot) {
+    pc := UInt(0)
+  } .otherwise {
+    switch(op) {
+      is(add_op) { rc := ra +% rb }
+      is(imm_op) { rc := (rai << 8) | rbi }
+    }
+    io.out := rc
+    when (rci === UInt(255)) {
+      io.valid := Bool(true)
+    } .otherwise {
+      file(rci) := rc
+    }
+    pc := pc +% UInt(1)
+  }
+}
+
+/*
+class RiscTester(c: Risc) extends Tester(c) {
+  def wr(addr: BigInt, data: BigInt)  = {
+    poke(c.io.isWr,   1)
+    poke(c.io.wrAddr, addr)
+    poke(c.io.wrData, data)
+    step(1)
+  }
+  def boot()  = {
+    poke(c.io.isWr, 0)
+    poke(c.io.boot, 1)
+    step(1)
+  }
+  def tick(isBoot: Boolean)  = {
+    if (isBoot)
+      poke(c.io.boot, 0)
+    step(1)
+  }
+  def I (op: UInt, rc: Int, ra: Int, rb: Int) = {
+    // val cr = Cat(op, UInt(rc, 8), UInt(ra, 8), UInt(rb, 8)).litValue()
+    val cr = op.litValue() << 24 | rc << 16 | ra << 8 | rb
+    println("I = " + cr)
+    cr
+  }
+
+  val app  = Array(I(c.imm_op,   1, 0, 1), // r1 <- 1
+                   I(c.add_op,   1, 1, 1), // r1 <- r1 + r1
+                   I(c.add_op,   1, 1, 1), // r1 <- r1 + r1
+                   I(c.add_op, 255, 1, 0)) // rh <- r1
+  wr(0, 0) // skip reset
+  for (addr <- 0 until app.length) 
+    wr(addr, app(addr))
+  def dump(k: Int) {
+    println("K = " + k)
+    peek(c.ra)
+    peek(c.rb)
+    peek(c.rc)
+    peek(c.io.out)
+    peek(c.pc)
+    peek(c.inst)
+    peek(c.op)
+    peek(c.rci)
+    peek(c.rai)
+    peek(c.rbi)
+    peekAt(c.file, 1)
+  }
+  boot()
+  dump(0)
+  var k = 0
+  do {
+    tick(k == 0); k += 1
+    dump(k)
+  } while (!(peek(c.io.valid) == 1 || k > 10))
+  expect(k <= 10, "TIME LIMIT")
+  expect(c.io.out, 4)
+}
+*/
+
+class RiscSpec extends ChiselPropSpec {
+  
+  property("Risc should elaborate") {
+    elaborate { new Risc }
+  }
+
+  ignore("RiscTester should return the correct result") { }
+}
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
new file mode 100644
index 00000000..4a87a2d2
--- /dev/null
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -0,0 +1,92 @@
+// See LICENSE for license details.
+
+package chiselTests
+import Chisel._
+import Chisel.testers.BasicTester
+
+class SIntOps extends Module {
+  val io = new Bundle {
+    val a = SInt(INPUT, 16)
+    val b = SInt(INPUT, 16)
+    val addout = SInt(OUTPUT, 16)
+    val subout = SInt(OUTPUT, 16)
+    val timesout = SInt(OUTPUT, 16)
+    val divout = SInt(OUTPUT, 16)
+    val modout = SInt(OUTPUT, 16)
+    val lshiftout = SInt(OUTPUT, 16)
+    val rshiftout = SInt(OUTPUT, 16)
+    val lessout = Bool(OUTPUT)
+    val greatout = Bool(OUTPUT)
+    val eqout = Bool(OUTPUT)
+    val noteqout = Bool(OUTPUT)
+    val lesseqout = Bool(OUTPUT)
+    val greateqout = Bool(OUTPUT)
+    val negout = SInt(OUTPUT, 16)
+  }
+
+  val a = io.a
+  val b = io.b
+
+  io.addout := a +% b
+  io.subout := a -% b
+  // TODO: 
+  //io.timesout := (a * b)(15, 0)
+  //io.divout := a / Mux(b === SInt(0), SInt(1), b)
+  //io.divout := (a / b)(15, 0)
+  //io.modout := SInt(0)
+  //io.lshiftout := (a << 12)(15, 0) //  (a << ub(3, 0))(15, 0).toSInt
+  io.rshiftout := (a >> 8) // (a >> ub).toSInt
+  io.lessout := a < b
+  io.greatout := a > b
+  io.eqout := a === b
+  io.noteqout := (a != b)
+  io.lesseqout := a <= b
+  io.greateqout := a >= b
+  // io.negout := -a(15, 0).toSInt
+  io.negout := (SInt(0) -% a)
+}
+
+/*
+class SIntOpsTester(c: SIntOps) extends Tester(c) {
+  def sintExpect(d: Bits, x: BigInt) {
+    val mask = (1 << 16) - 1
+    val sbit = (1 << 15)
+    val y = x & mask
+    val r = if ((y & sbit) == 0) y else (-(~y)-1)
+    expect(d, r)
+  }
+  for (t <- 0 until 16) {
+    val test_a = (1 << 15) - rnd.nextInt(1 << 16)
+    val test_b = (1 << 15) - rnd.nextInt(1 << 16)
+    poke(c.io.a, test_a)
+    poke(c.io.b, test_b)
+    step(1)
+    sintExpect(c.io.addout, test_a + test_b)
+    sintExpect(c.io.subout, test_a - test_b)
+    sintExpect(c.io.timesout, test_a * test_b)
+    // sintExpect(c.io.divout, if (test_b == 0) 0 else test_a / test_b)
+    sintExpect(c.io.divout, test_a * test_b)
+    // sintExpect(c.io.modout, test_a % test_b)
+    // sintExpect(c.io.lshiftout, test_a << (test_b&15))
+    // sintExpect(c.io.rshiftout, test_a >> test_b)
+    sintExpect(c.io.lshiftout, test_a << 12)
+    sintExpect(c.io.rshiftout, test_a >> 8)
+    sintExpect(c.io.negout, -test_a)
+    expect(c.io.lessout, int(test_a < test_b))
+    expect(c.io.greatout, int(test_a > test_b))
+    expect(c.io.eqout, int(test_a == test_b))
+    expect(c.io.noteqout, int(test_a != test_b))
+    expect(c.io.lessout, int(test_a <= test_b))
+    expect(c.io.greateqout, int(test_a >= test_b))
+  }
+}
+*/
+
+class SIntOpsSpec extends ChiselPropSpec {
+  
+  property("SIntOps should elaborate") {
+    elaborate { new SIntOps }
+  }
+
+  ignore("SIntOpsTester should return the correct result") { }
+}
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
new file mode 100644
index 00000000..0110550d
--- /dev/null
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -0,0 +1,75 @@
+// See LICENSE for license details.
+
+package chiselTests
+import scala.collection.mutable.Stack
+import Chisel._
+
+class ChiselStack(val depth: Int) extends Module {
+  val io = new Bundle {
+    val push    = Bool(INPUT)
+    val pop     = Bool(INPUT)
+    val en      = Bool(INPUT)
+    val dataIn  = UInt(INPUT,  32)
+    val dataOut = UInt(OUTPUT, 32)
+  }
+
+  val stack_mem = Mem(UInt(width = 32), depth)
+  val sp        = Reg(init = UInt(0, width = log2Up(depth+1)))
+  val out       = Reg(init = UInt(0, width = 32))
+
+  when (io.en) {
+    when(io.push && (sp < UInt(depth))) {
+      stack_mem(sp) := io.dataIn
+      sp := sp +% UInt(1)
+    } .elsewhen(io.pop && (sp > UInt(0))) {
+      sp := sp -% UInt(1)
+    }
+    when (sp > UInt(0)) {
+      out := stack_mem(sp -% UInt(1))
+    }
+  }
+  io.dataOut := out
+}
+
+/*
+class StackTester(c: Stack) extends Tester(c) {
+  var nxtDataOut = 0
+  var dataOut = 0
+  val stack = new ScalaStack[Int]()
+
+  for (t <- 0 until 16) {
+    val enable  = rnd.nextInt(2)
+    val push    = rnd.nextInt(2)
+    val pop     = rnd.nextInt(2)
+    val dataIn  = rnd.nextInt(256)
+
+    if (enable == 1) {
+      dataOut = nxtDataOut
+      if (push == 1 && stack.length < c.depth) {
+        stack.push(dataIn)
+      } else if (pop == 1 && stack.length > 0) {
+        stack.pop()
+      }
+      if (stack.length > 0) {
+        nxtDataOut = stack.top
+      }
+    }
+
+    poke(c.io.pop,    pop)
+    poke(c.io.push,   push)
+    poke(c.io.en,     enable)
+    poke(c.io.dataIn, dataIn)
+    step(1)
+    expect(c.io.dataOut, dataOut)
+  }
+}
+*/
+
+class StackSpec extends ChiselPropSpec {
+  
+  property("Stack should elaborate") {
+    elaborate { new ChiselStack(2) }
+  }
+
+  ignore("StackTester should return the correct result") { }
+}
diff --git a/src/test/scala/chiselTests/UInt.scala b/src/test/scala/chiselTests/UInt.scala
deleted file mode 100644
index 3c5e1ab7..00000000
--- a/src/test/scala/chiselTests/UInt.scala
+++ /dev/null
@@ -1,34 +0,0 @@
-// See LICENSE for license details.
-
-package chiselTests
-
-import Chisel._
-import org.scalatest._
-import org.scalatest.prop._
-import Chisel.testers.BasicTester
-
-class GoodBoolConversion extends Module {
-  val io = new Bundle {
-    val u = UInt(1, width = 1).asInput
-    val b = Bool(OUTPUT)
-  }
-  io.b := io.u.toBool
-}
-
-class BadBoolConversion extends Module {
-  val io = new Bundle {
-    val u = UInt(1, width = 5).asInput
-    val b = Bool(OUTPUT)
-  }
-  io.b := io.u.toBool
-}
-
-class UIntSpec extends ChiselPropSpec with Matchers {
-  property("Bools can be created from 1 bit UInts") {
-    elaborate(new GoodBoolConversion)
-  }
-
-  property("Bools cannot be created from >1 bit UInts") {
-    a [Exception] should be thrownBy { elaborate(new BadBoolConversion) }
-  }
-}
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
new file mode 100644
index 00000000..9affb511
--- /dev/null
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -0,0 +1,109 @@
+// See LICENSE for license details.
+
+package chiselTests
+import Chisel._
+import org.scalatest._
+import Chisel.testers.BasicTester
+
+class UIntOps extends Module {
+  val io = new Bundle {
+    val a = UInt(INPUT, 16)
+    val b = UInt(INPUT, 16)
+    val addout = UInt(OUTPUT, 16)
+    val subout = UInt(OUTPUT, 16)
+    val timesout = UInt(OUTPUT, 16)
+    val divout = UInt(OUTPUT, 16)
+    val modout = UInt(OUTPUT, 16)
+    val lshiftout = UInt(OUTPUT, 16)
+    val rshiftout = UInt(OUTPUT, 16)
+    val lessout = Bool(OUTPUT)
+    val greatout = Bool(OUTPUT)
+    val eqout = Bool(OUTPUT)
+    val noteqout = Bool(OUTPUT)
+    val lesseqout = Bool(OUTPUT)
+    val greateqout = Bool(OUTPUT)
+  }
+
+  val a = io.a
+  val b = io.b
+
+  io.addout := a +% b
+  io.subout := a -% b
+  io.timesout := (a * b)(15, 0)
+  io.divout := a / Mux(b === UInt(0), UInt(1), b)
+  // io.modout := a % b
+  // TODO: 
+  io.modout := UInt(0)
+  io.lshiftout := (a << b(3, 0))(15, 0)
+  io.rshiftout := a >> b
+  io.lessout := a < b
+  io.greatout := a > b
+  io.eqout := a === b
+  io.noteqout := (a != b)
+  io.lesseqout := a <= b
+  io.greateqout := a >= b
+}
+
+/*
+class UIntOpsTester(c: UIntOps) extends Tester(c) {
+  def uintExpect(d: Bits, x: BigInt) {
+    val mask = (1 << 16) - 1
+    println(" E = " + x + " X&M = " + (x & mask))
+    expect(d, x & mask)
+  }
+  for (t <- 0 until 16) {
+    val test_a = rnd.nextInt(1 << 16)
+    val test_b = rnd.nextInt(1 << 16)
+    println("A = " + test_a + " B = " + test_b)
+    poke(c.io.a, test_a)
+    poke(c.io.b, test_b)
+    step(1)
+    uintExpect(c.io.addout, test_a + test_b)
+    uintExpect(c.io.subout, test_a - test_b)
+    uintExpect(c.io.divout, if (test_b == 0) 0 else test_a / test_b)
+    uintExpect(c.io.timesout, test_a * test_b)
+    // uintExpect(c.io.modout, test_a % test_b)
+    uintExpect(c.io.lshiftout, test_a << (test_b&15))
+    uintExpect(c.io.rshiftout, test_a >> test_b)
+    expect(c.io.lessout, int(test_a < test_b))
+    expect(c.io.greatout, int(test_a > test_b))
+    expect(c.io.eqout, int(test_a == test_b))
+    expect(c.io.noteqout, int(test_a != test_b))
+    expect(c.io.lessout, int(test_a <= test_b))
+    expect(c.io.greateqout, int(test_a >= test_b))
+  }
+}
+*/
+
+class GoodBoolConversion extends Module {
+  val io = new Bundle {
+    val u = UInt(1, width = 1).asInput
+    val b = Bool(OUTPUT)
+  }
+  io.b := io.u.toBool
+}
+
+class BadBoolConversion extends Module {
+  val io = new Bundle {
+    val u = UInt(1, width = 5).asInput
+    val b = Bool(OUTPUT)
+  }
+  io.b := io.u.toBool
+}
+
+class UIntOpsSpec extends ChiselPropSpec with Matchers {
+  property("Bools can be created from 1 bit UInts") {
+    elaborate(new GoodBoolConversion)
+  }
+
+  property("Bools cannot be created from >1 bit UInts") {
+    a [Exception] should be thrownBy { elaborate(new BadBoolConversion) }
+  }
+  
+  property("UIntOps should elaborate") {
+    elaborate { new UIntOps }
+  }
+
+  ignore("UIntOpsTester should return the correct result") { }
+}
+
diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala
new file mode 100644
index 00000000..8a21cb2e
--- /dev/null
+++ b/src/test/scala/chiselTests/VendingMachine.scala
@@ -0,0 +1,67 @@
+// See LICENSE for license details.
+
+package chiselTests
+import Chisel._
+
+class VendingMachine extends Module {
+  val io = new Bundle {
+    val nickel = Bool(dir = INPUT)
+    val dime   = Bool(dir = INPUT)
+    val valid  = Bool(dir = OUTPUT) }
+  val c = UInt(5, width = 3)
+  val sIdle :: s5 :: s10 :: s15 :: sOk :: Nil = Enum(UInt(), 5)
+  val state = Reg(init = sIdle)
+  when (state === sIdle) {
+    when (io.nickel) { state := s5 }
+    when (io.dime)   { state := s10 }
+  }
+  when (state === s5) {
+    when (io.nickel) { state := s10 }
+    when (io.dime)   { state := s15 }
+  }
+  when (state === s10) {
+    when (io.nickel) { state := s15 }
+    when (io.dime)   { state := sOk }
+  }
+  when (state === s15) {
+    when (io.nickel) { state := sOk }
+    when (io.dime)   { state := sOk }
+  }
+  when (state === sOk) {
+    state := sIdle
+  }
+  io.valid := (state === sOk)
+}
+
+/*
+class VendingMachineTester(c: VendingMachine) extends Tester(c) {
+  var money = 0
+  var isValid = false
+  for (t <- 0 until 20) {
+    val coin     = rnd.nextInt(3)*5
+    val isNickel = coin == 5
+    val isDime   = coin == 10
+
+    // Advance circuit
+    poke(c.io.nickel, int(isNickel))
+    poke(c.io.dime,   int(isDime))
+    step(1)
+
+    // Advance model
+    money = if (isValid) 0 else (money + coin)
+    isValid = money >= 20
+
+    // Compare
+    expect(c.io.valid, int(isValid))
+  }
+}
+*/
+
+class VendingMachineSpec extends ChiselPropSpec {
+  
+  property("VendingMachine should elaborate") {
+    elaborate { new VendingMachine }
+  }
+
+  ignore("VendingMachineTester should return the correct result") { }
+}