| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2021-07-28 | Fixes from lfcode.cariscv | Aditya Naik | |
| PMP enforecement from Qemu breaks boot cycle. This fix is from upstream repo here: https://github.com/lf-/xv6-riscv/ | |||
| 2020-10-05 | more explicable scratch area size for machine-mode timer interrupts | Robert Morris | |
| 2019-10-27 | nits | Robert Morris | |
| 2019-07-28 | separate out timer init code for clarity | Robert Morris | |
| 2019-07-26 | machinevec -> timervec | Robert Morris | |
| 2019-07-25 | fix an exit/exit deadlock -> one more locking protocol violation | Robert Morris | |
| increase timer rate from 1/second to 10/second | |||
| 2019-07-25 | comments for timer setup | Robert Morris | |
| 2019-07-23 | mstart -> start | Robert Morris | |
| 2019-06-11 | separate source into kernel/ user/ mkfs/ | Robert Morris | |
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index : xv6-riscv | |
| MIT xv6-RISCV kernel modified to RV64I base integer extension | Aditya N. Naik |
| summaryrefslogtreecommitdiff |