diff options
| author | Aditya Naik | 2021-07-28 02:43:40 -0400 |
|---|---|---|
| committer | Aditya Naik | 2021-07-28 02:43:40 -0400 |
| commit | 29ca76b95eeb130b65f37824ff36bcb1b25356bd (patch) | |
| tree | d56e0fab3289aab34cbc4a052b16b5e4609581c4 /kernel/start.c | |
| parent | 951e300c10613c8500705d7b54467169be53a7f5 (diff) | |
Fixes from lfcode.cariscv
PMP enforecement from Qemu breaks boot cycle. This fix is from
upstream repo here: https://github.com/lf-/xv6-riscv/
Diffstat (limited to 'kernel/start.c')
| -rw-r--r-- | kernel/start.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/kernel/start.c b/kernel/start.c index 1876680..2d89d90 100644 --- a/kernel/start.c +++ b/kernel/start.c @@ -44,7 +44,16 @@ start() // keep each CPU's hartid in its tp register, for cpuid(). int id = r_mhartid(); w_tp(id); - + + // allow access to all physical memory by S mode + // see figure 3.27 "PMP address register format, RV64" and table 3.10 "NAPOT + // range encoding in PMP address and configuration registers" in the RISC-V + // privileged specification + // we set the bits such that this matches any 56-bit physical address + w_pmpaddr0((~0ULL) >> 10); + // then we allow the access + w_pmpcfg0(PMP_R | PMP_W | PMP_X | PMP_MATCH_NAPOT); + // switch to supervisor mode and jump to main(). asm volatile("mret"); } |
