diff options
| author | Aditya Naik | 2021-07-28 02:43:40 -0400 |
|---|---|---|
| committer | Aditya Naik | 2021-07-28 02:43:40 -0400 |
| commit | 29ca76b95eeb130b65f37824ff36bcb1b25356bd (patch) | |
| tree | d56e0fab3289aab34cbc4a052b16b5e4609581c4 /kernel/riscv.h | |
| parent | 951e300c10613c8500705d7b54467169be53a7f5 (diff) | |
Fixes from lfcode.cariscv
PMP enforecement from Qemu breaks boot cycle. This fix is from
upstream repo here: https://github.com/lf-/xv6-riscv/
Diffstat (limited to 'kernel/riscv.h')
| -rw-r--r-- | kernel/riscv.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/kernel/riscv.h b/kernel/riscv.h index 0aec003..25614b1 100644 --- a/kernel/riscv.h +++ b/kernel/riscv.h @@ -38,6 +38,29 @@ w_mepc(uint64 x) asm volatile("csrw mepc, %0" : : "r" (x)); } +// physical memory protection CSRs +#define PMP_R (1L << 0) +#define PMP_W (1L << 1) +#define PMP_X (1L << 2) +// naturally aligned power of two +#define PMP_MATCH_NAPOT (3L << 3) + +// we only implement accessing one PMP register + +// write to the first 8 PMP configuration registers +static inline void +w_pmpcfg0(uint64 x) +{ + asm volatile("csrw pmpcfg0, %0" : : "r" (x)); +} + +// write to the address for PMP region 0 +static inline void +w_pmpaddr0(uint64 x) +{ + asm volatile("csrw pmpaddr0, %0" : : "r" (x)); +} + // Supervisor Status Register, sstatus #define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User |
