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AgeCommit message (Expand)Author
2020-06-24Module DC handlerAditya Naik
2020-06-22Optimizations for master data and command routing handling and corresponding ...Aditya Naik
2020-06-18This CL adds support for dataflow branch 2, which includes master processing ...Aditya Naik
2020-06-15I2C speed upgrade for master and slaveAditya Naik
2020-06-15Ports mergeAditya Naik
2020-06-11Added UART device initialization for new dev boardAditya Naik
2020-06-10Moved all F4-specific files to the HAL port directoryAditya Naik
2020-06-09Added port files for STM32F405RG and minor address change to slaveAditya Naik
2020-06-09Moved nanopb files to library dir; changed main filenamesAditya Naik
2020-06-08Routing bugfixAditya Naik
2020-06-08This CL adds a major refactor to the protocol implementation by moving away f...Aditya Naik
2020-06-01Renamed master and slave files, small edits to codeAditya Naik
2020-05-28Added slave file, handshake to slaveAditya Naik
2020-05-28This CL adds bookkeeping structures for routing, including the routing buffer...Aditya Naik
2020-05-14This CL adds structures for bookkeeping for dataflow based on the dataflow pr...Aditya Naik
2020-04-22Added dataflow protocol filesAditya Naik
2020-04-22Manually added MDRAditya Naik
2020-04-22Manually add MDRAditya Naik
2020-04-22Better idea: treat hs as done, manually add MDRAditya Naik
2020-04-22Better idea: treat hs as done, manually add MDRAditya Naik
2020-04-21New working main fileAditya Naik
2020-04-09Master roggleAditya Naik
2020-04-09main.c and corresponding makefileAditya Naik
2020-04-09Added cient code to master hsAditya Naik
2020-04-09Added cient code to master hsAditya Naik
2020-04-09Project refactorAditya Naik
2020-03-24Initial working MDR request, now ACKAditya Naik
2020-03-23InitialAditya Naik
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