blob: d790272ccae26d9ca362480f795a00e82968def0 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
|
; RUN: firrtl %s abcdef cg | tee %s.out | FileCheck %s
;CHECK: Resolve Genders
circuit top :
module source :
output data : UInt(16)
input ready : UInt(1)
data := UInt(16)
module sink :
input data : UInt(16)
output ready : UInt(1)
module top:
wire connect : { data : UInt(16), flip ready: UInt(1) }
inst src of source ;CHECK: inst src of source@<g:female>
inst snk of sink ;CHECK: inst snk of sink@<g:female>
connect.data := src.data ;CHECK: connect@<g:female>.data@<g:female> := src@<g:female>.data@<g:male>
src.ready := connect.ready ;CHECK: src@<g:female>.ready@<g:female> := connect@<g:female>.ready@<g:male>
snk.data := connect.data ;CHECK: snk@<g:female>.data@<g:female> := connect@<g:male>.data@<g:male>
connect.ready := snk.ready ;CHECK: connect@<g:male>.ready@<g:female> := snk@<g:female>.ready@<g:male>
; CHECK: Finished Resolve Genders
|
