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; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
; CHECK: Expand Whens
circuit BundleWire :
module BundleWire :
input in : { y : UInt<32>, x : UInt<32> }
output outs : { y : UInt<32>, x : UInt<32> }[4]
wire coords : { y : UInt<32>, x : UInt<32> }[4]
coords[0] := in
outs[0] := coords[0]
coords[1] := in
outs[1] := coords[1]
coords[2] := in
outs[2] := coords[2]
coords[3] := in
outs[3] := coords[3]
; CHECK: Finished Expand Whens
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