blob: 718f1d4bff280111dab907a3384f38d3e0177e8a (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
|
; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
; CHECK: Expand Whens
circuit top :
module top :
mem m : UInt<1>[2]
wire i : UInt<1>
wire p : UInt<1>
wire j : UInt<1>
reg r : UInt<1>
p := j
when p :
on-reset r := i
accessor a = m[i]
i := a
accessor b = m[i]
b := i
else :
accessor c = m[i]
i := c
accessor d = m[i]
d := i
accessor e = m[i]
when p :
p := i
when e :
p := p
on-reset r := p
r := p
; CHECK: Finished Expand Whens
|
