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; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
; XFAIL: *
; CHECK: Expand Indexed Connects
circuit top :
module top :
wire outs : UInt<32>[2][1]
outs[0][0] := UInt(1)
outs[0][1] := UInt(1)
write accessor out = outs[UInt(0)]
out[0] := UInt(1)
; CHECK: Done!
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