aboutsummaryrefslogtreecommitdiff
path: root/test/integration/MemTester.fir
blob: 68e085441a3eb07b890ca2bf7d1cbf03bea2925d (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
; SPDX-License-Identifier: Apache-2.0
circuit MemTester :
  module ReadWrite :
    input clock : Clock
    input reset : UInt<1>

    reg n : UInt<32>, clock with :
      reset => (reset, UInt(0))

    reg wmode : UInt<1>, clock with :
      reset => (reset, UInt(1))
    wmode <= not(wmode)

    reg addr : UInt<5>, clock with :
      reset => (reset, UInt(0))

    when eq(wmode, UInt(0)) :
      n <= add(n, UInt(1))
      addr <= add(addr, UInt(1))

    mem m :
      data-type => UInt<32>
      depth => 32
      read-latency => 0
      write-latency => 1
      readwriter => rw
      read-under-write => undefined
    m.rw.clk <= clock
    m.rw.addr <= addr
    m.rw.wmode <= wmode
    m.rw.wdata <= n
    m.rw.wmask <= UInt(1)
    m.rw.en <= UInt(1)

    when not(reset) :
      when eq(wmode, UInt(0)) :
        when neq(m.rw.rdata, n) :
          printf(clock, UInt(1), "Assertion failed! m.rw.rdata has the wrong value!\n")
          stop(clock, UInt(1), 1)

  module MemTester :
    input clock : Clock
    input reset : UInt<1>

    reg count : UInt<32>, clock with :
      reset => (reset, UInt(100))
    count <= tail(sub(count, UInt(1)), 1)

    inst rwMod of ReadWrite
    rwMod.clock <= clock
    rwMod.reset <= reset

    when eq(count, UInt(0)) :
      stop(clock, UInt(1), 0)