blob: 9060d70503a6a62ccbdea1ac1cca94c274b71ff7 (
plain)
1
2
3
4
5
6
7
8
9
10
|
; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s
circuit Top :
module Top :
node x = UInt("h2")
node y = UInt("h100000")
node z = UInt("h00")
;CHECK: node x = UInt<2>("h2")
;CHECK: node z = UInt<1>("h0")
;CHECK: Done!
|
