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; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
; CHECK: Invalid index access to non-reference.
; CHECK: Invalid subfield access to non-reference.
circuit Top :
module Top :
wire x : UInt<4>
add(x,x)[10] <= UInt(1)
add(x,x).x <= UInt(1)
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