1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
|
// SPDX-License-Identifier: Apache-2.0
package firrtlTests
package transforms
import firrtl.annotations.{CircuitName, ComponentName, ModuleName}
import firrtl.transforms.{GroupAnnotation, GroupComponents, NoCircuitDedupAnnotation}
import firrtl._
import firrtl.ir._
import firrtl.testutils._
import FirrtlCheckers._
class GroupComponentsSpec extends MiddleTransformSpec {
def transform = new GroupComponents()
val top = "Top"
def topComp(name: String): ComponentName = ComponentName(name, ModuleName(top, CircuitName(top)))
"The register r" should "be grouped" in {
val input =
s"""circuit $top :
| module $top :
| input clk: Clock
| input data: UInt<16>
| output out: UInt<16>
| reg r: UInt<16>, clk
| r <= data
| out <= r
""".stripMargin
val groups = Seq(
GroupAnnotation(Seq(topComp("r")), "MyReg", "rInst", Some("_OUT"), Some("_IN"))
)
val check =
s"""circuit Top :
| module $top :
| input clk: Clock
| input data: UInt<16>
| output out: UInt<16>
| inst rInst of MyReg
| rInst.clk_IN <= clk
| out <= rInst.r_OUT
| rInst.data_IN <= data
| module MyReg :
| input clk_IN: Clock
| output r_OUT: UInt<16>
| input data_IN: UInt<16>
| reg r: UInt<16>, clk_IN
| r_OUT <= r
| r <= data_IN
""".stripMargin
execute(input, check, groups)
}
"Grouping" should "work even when there are unused nodes" in {
val input =
s"""circuit $top :
| module $top :
| input in: UInt<16>
| output out: UInt<16>
| node n = UInt<16>("h0")
| wire w : UInt<16>
| wire a : UInt<16>
| wire b : UInt<16>
| a <= UInt<16>("h0")
| b <= a
| w <= in
| out <= w
""".stripMargin
val groups = Seq(
GroupAnnotation(Seq(topComp("w")), "Child", "inst", Some("_OUT"), Some("_IN"))
)
val check =
s"""circuit Top :
| module $top :
| input in: UInt<16>
| output out: UInt<16>
| inst inst of Child
| node n = UInt<16>("h0")
| wire a : UInt<16>
| wire b : UInt<16>
| out <= inst.w_OUT
| inst.in_IN <= in
| a <= UInt<16>("h0")
| b <= a
| module Child :
| output w_OUT : UInt<16>
| input in_IN : UInt<16>
| wire w : UInt<16>
| w_OUT <= w
| w <= in_IN
""".stripMargin
execute(input, check, groups)
}
"The two sets of instances" should "be grouped" in {
val input =
s"""circuit $top :
| module $top :
| output out: UInt<16>
| inst c1a of Const1A
| inst c2a of Const2A
| inst c1b of Const1B
| inst c2b of Const2B
| node asum = add(c1a.out, c2a.out)
| node bsum = add(c1b.out, c2b.out)
| out <= add(asum, bsum)
| module Const1A :
| output out: UInt<8>
| out <= UInt(1)
| module Const2A :
| output out: UInt<8>
| out <= UInt(2)
| module Const1B :
| output out: UInt<8>
| out <= UInt(1)
| module Const2B :
| output out: UInt<8>
| out <= UInt(2)
""".stripMargin
val annotations = Seq(
GroupAnnotation(Seq(topComp("c1a"), topComp("c2a") /*, topComp("asum")*/ ), "A", "cA", Some("_OUT"), Some("_IN")),
GroupAnnotation(Seq(topComp("c1b"), topComp("c2b") /*, topComp("bsum")*/ ), "B", "cB", Some("_OUT"), Some("_IN")),
NoCircuitDedupAnnotation
)
val check =
s"""circuit Top :
| module $top :
| output out: UInt<16>
| inst cA of A
| inst cB of B
| node asum = add(cA.c1a_out_OUT, cA.c2a_out_OUT)
| node bsum = add(cB.c1b_out_OUT, cB.c2b_out_OUT)
| out <= add(asum, bsum)
| module A :
| output c1a_out_OUT: UInt<8>
| output c2a_out_OUT: UInt<8>
| inst c1a of Const1A
| inst c2a of Const2A
| c1a_out_OUT <= c1a.out
| c2a_out_OUT <= c2a.out
| module B :
| output c1b_out_OUT: UInt<8>
| output c2b_out_OUT: UInt<8>
| inst c1b of Const1B
| inst c2b of Const2B
| c1b_out_OUT <= c1b.out
| c2b_out_OUT <= c2b.out
| module Const1A :
| output out: UInt<8>
| out <= UInt(1)
| module Const2A :
| output out: UInt<8>
| out <= UInt(2)
| module Const1B :
| output out: UInt<8>
| out <= UInt(1)
| module Const2B :
| output out: UInt<8>
| out <= UInt(2)
""".stripMargin
execute(input, check, annotations)
}
"The two sets of instances" should "be grouped with their nodes" in {
val input =
s"""circuit $top :
| module $top :
| output out: UInt<16>
| inst c1a of Const1A
| inst c2a of Const2A
| inst c1b of Const1B
| inst c2b of Const2B
| node asum = add(c1a.out, c2a.out)
| node bsum = add(c1b.out, c2b.out)
| out <= add(asum, bsum)
| module Const1A :
| output out: UInt<8>
| out <= UInt(1)
| module Const2A :
| output out: UInt<8>
| out <= UInt(2)
| module Const1B :
| output out: UInt<8>
| out <= UInt(1)
| module Const2B :
| output out: UInt<8>
| out <= UInt(2)
""".stripMargin
val annotations = Seq(
GroupAnnotation(Seq(topComp("c1a"), topComp("c2a"), topComp("asum")), "A", "cA", Some("_OUT"), Some("_IN")),
GroupAnnotation(Seq(topComp("c1b"), topComp("c2b"), topComp("bsum")), "B", "cB", Some("_OUT"), Some("_IN")),
NoCircuitDedupAnnotation
)
val check =
s"""circuit Top :
| module $top :
| output out: UInt<16>
| inst cA of A
| inst cB of B
| out <= add(cA.asum_OUT, cB.bsum_OUT)
| module A :
| output asum_OUT: UInt<9>
| inst c1a of Const1A
| inst c2a of Const2A
| node asum = add(c1a.out, c2a.out)
| asum_OUT <= asum
| module B :
| output bsum_OUT: UInt<9>
| inst c1b of Const1B
| inst c2b of Const2B
| node bsum = add(c1b.out, c2b.out)
| bsum_OUT <= bsum
| module Const1A :
| output out: UInt<8>
| out <= UInt(1)
| module Const2A :
| output out: UInt<8>
| out <= UInt(2)
| module Const1B :
| output out: UInt<8>
| out <= UInt(1)
| module Const2B :
| output out: UInt<8>
| out <= UInt(2)
""".stripMargin
execute(input, check, annotations)
}
"The two sets of instances" should "be grouped with one not grouped" in {
val input =
s"""circuit $top :
| module $top :
| output out: UInt<16>
| inst c1a of Const1A
| inst c2a of Const2A
| inst c1b of Const1B
| inst c2b of Const2B
| node asum = add(c1a.out, c2a.out)
| node bsum = add(c1b.out, c2b.out)
| inst pass of PassThrough
| pass.in <= add(asum, bsum)
| out <= pass.out
| module Const1A :
| output out: UInt<8>
| out <= UInt(1)
| module Const2A :
| output out: UInt<8>
| out <= UInt(2)
| module Const1B :
| output out: UInt<8>
| out <= UInt(1)
| module Const2B :
| output out: UInt<8>
| out <= UInt(2)
| module PassThrough :
| input in: UInt
| output out: UInt
| out <= in
""".stripMargin
val annotations = Seq(
GroupAnnotation(Seq(topComp("c1a"), topComp("c2a"), topComp("asum")), "A", "cA", Some("_OUT"), Some("_IN")),
GroupAnnotation(Seq(topComp("c1b"), topComp("c2b"), topComp("bsum")), "B", "cB", Some("_OUT"), Some("_IN")),
NoCircuitDedupAnnotation
)
val check =
s"""circuit Top :
| module $top :
| output out: UInt<16>
| inst cA of A
| inst cB of B
| inst pass of PassThrough
| out <= pass.out
| pass.in <= add(cA.asum_OUT, cB.bsum_OUT)
| module A :
| output asum_OUT: UInt<9>
| inst c1a of Const1A
| inst c2a of Const2A
| node asum = add(c1a.out, c2a.out)
| asum_OUT <= asum
| module B :
| output bsum_OUT: UInt<9>
| inst c1b of Const1B
| inst c2b of Const2B
| node bsum = add(c1b.out, c2b.out)
| bsum_OUT <= bsum
| module Const1A :
| output out: UInt<8>
| out <= UInt(1)
| module Const2A :
| output out: UInt<8>
| out <= UInt(2)
| module Const1B :
| output out: UInt<8>
| out <= UInt(1)
| module Const2B :
| output out: UInt<8>
| out <= UInt(2)
| module PassThrough :
| input in: UInt<10>
| output out: UInt<10>
| out <= in
""".stripMargin
execute(input, check, annotations)
}
"The two sets of instances" should "be grouped with a connection between them" in {
val input =
s"""circuit $top :
| module $top :
| input in: UInt<16>
| output out: UInt<16>
| node first = in
| node second = not(first)
| out <= second
""".stripMargin
val groups = Seq(
GroupAnnotation(Seq(topComp("first")), "First", "first"),
GroupAnnotation(Seq(topComp("second")), "Second", "second")
)
val check =
s"""circuit $top :
| module $top :
| input in: UInt<16>
| output out: UInt<16>
| inst first_0 of First
| inst second_0 of Second
| first_0.in <= in
| second_0.first <= first_0.first_0
| out <= second_0.second_0
| module First :
| input in: UInt<16>
| output first_0: UInt<16>
| node first = in
| first_0 <= first
| module Second :
| input first: UInt<16>
| output second_0: UInt<16>
| node second = not(first)
| second_0 <= second
""".stripMargin
execute(input, check, groups)
}
"Instances with uninitialized ports" should "work properly" in {
val input =
s"""circuit $top :
| module $top :
| input in: UInt<16>
| output out: UInt<16>
| inst other of Other
| other is invalid
| out <= add(in, other.out)
| module Other:
| input in: UInt<16>
| output out: UInt<16>
| out <= add(asUInt(in), UInt(1))
""".stripMargin
val groups = Seq(
GroupAnnotation(Seq(topComp("other")), "Wrapper", "wrapper")
)
val check =
s"""circuit $top :
| module $top :
| input in: UInt<16>
| output out: UInt<16>
| inst wrapper of Wrapper
| out <= add(in, wrapper.other_out)
| module Wrapper :
| output other_out: UInt<16>
| inst other of Other
| other_out <= other.out
| other.in is invalid
| module Other:
| input in: UInt<16>
| output out: UInt<16>
| out <= add(asUInt(in), UInt(1))
""".stripMargin
execute(input, check, groups)
}
}
class GroupComponentsIntegrationSpec extends FirrtlFlatSpec {
def topComp(name: String): ComponentName = ComponentName(name, ModuleName("Top", CircuitName("Top")))
"Grouping" should "properly set kinds" in {
val input =
"""circuit Top :
| module Top :
| input clk: Clock
| input data: UInt<16>
| output out: UInt<16>
| reg r: UInt<16>, clk
| r <= data
| out <= r
""".stripMargin
val groups = Seq(
GroupAnnotation(Seq(topComp("r")), "MyModule", "inst", Some("_OUT"), Some("_IN"))
)
val result = (new VerilogCompiler).compileAndEmit(
CircuitState(parse(input), ChirrtlForm, groups),
Seq(new GroupComponents)
)
result should containTree {
case Connect(_, WSubField(WRef("inst", _, InstanceKind, _), "data_IN", _, _), WRef("data", _, _, _)) => true
}
result should containTree {
case Connect(_, WSubField(WRef("inst", _, InstanceKind, _), "clk_IN", _, _), WRef("clk", _, _, _)) => true
}
result should containTree {
case Connect(_, WRef("out", _, _, _), WSubField(WRef("inst", _, InstanceKind, _), "r_OUT", _, _)) => true
}
}
}
|
