1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
|
// SPDX-License-Identifier: Apache-2.0
package firrtlTests.formal
import firrtl._
import firrtl.testutils.FirrtlFlatSpec
import firrtl.transforms.formal.ConvertAsserts
class ConvertAssertsSpec extends FirrtlFlatSpec {
val preamble =
"""circuit DUT:
| module DUT:
| input clock: Clock
| input reset: UInt<1>
| input x: UInt<8>
| output y: UInt<8>
| y <= x
| node ne5 = neq(x, UInt(5))
|""".stripMargin
"assert nodes" should "be converted to predicated prints and stops" in {
val input = preamble +
""" assert(clock, ne5, not(reset), "x should not equal 5")
|""".stripMargin
val ref = preamble +
""" printf(clock, and(not(ne5), not(reset)), "x should not equal 5") : assert_0_print
| stop(clock, and(not(ne5), not(reset)), 1) : assert_0
|""".stripMargin
val state = CircuitState(parse(input), Nil)
val outputCS = ConvertAsserts.execute(state)
(parse(outputCS.circuit.serialize)) should be(parse(ref))
}
"assert nodes with no message" should "omit printed messages" in {
val input = preamble +
""" assert(clock, ne5, not(reset), "")
|""".stripMargin
val ref = preamble +
""" stop(clock, and(not(ne5), not(reset)), 1) : assert_0
|""".stripMargin
val outputCS = ConvertAsserts.execute(CircuitState(parse(input), Nil))
(parse(outputCS.circuit.serialize)) should be(parse(ref))
}
}
|
